Patents Examined by S. M. S Imtiaz
  • Patent number: 10319757
    Abstract: A photoelectric conversion device includes a photoelectric conversion portion in a silicon layer having a light-receiving surface. The silicon layer includes a P-type impurity region including a base portion having an atomic boron concentration Ba that is the highest of the portions opposite the light-receiving surface with respect to a charge accumulation region and an atomic oxygen concentration Oa, and a deep portion located opposite the charge accumulation region in the depth direction with respect to the base portion and having an atomic boron concentration Bb and an atomic oxygen concentration Ob. The impurity region satisfies Ba×Oa2<Bb×Ob2.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: June 11, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Akira Ohtani, Tasuku Kaneda
  • Patent number: 10211091
    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: February 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myeong-Dong Lee, Keunnam Kim, Dongryul Lee, Minseong Choi, Jimin Choi, Yong Kwan Kim, Changhyun Cho, Yoosang Hwang
  • Patent number: 10193058
    Abstract: According to one embodiment, a magnetoresistive memory device includes a first magnetic layer, a second magnetic layer on one major surface side of the first magnetic layer via a first nonmagnetic layer, a third magnetic layer on the second magnetic layer via a first Ru layer, a sidewall insulating film on sides of the layers, a fourth magnetic layer on an other major surface side of the first magnetic layer via a second nonmagnetic layer, and a fifth magnetic layer on the fourth magnetic layer via a second Ru layer. The reversed magnetic field of the second magnetic layer is smaller than that of the third and fourth magnetic layers, and the reversed magnetic field of the fifth magnetic layer is smaller than that of the third and fourth magnetic layers.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: January 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masayoshi Iwayama
  • Patent number: 10186618
    Abstract: An object is to achieve high electrical characteristics (a high on-state current value, an excellent S value, and the like) and a highly reliable semiconductor device. A high on-state current value is achieved, whereby a further reduction in channel width (W) is achieved. A second conductive layer functioning as a gate electrode has a function of electrically surrounding side surfaces of a semiconductor film in a cross section in a channel width direction. With this structure, on-state current of a transistor can be increased. To achieve a semiconductor device with less hot-carrier degradation, the gate electrode has a tapered portion.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10181447
    Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 15, 2019
    Assignee: Invensas Corporation
    Inventors: Chok J. Chia, Qwai H. Low, Patrick Variot
  • Patent number: 10177241
    Abstract: One illustrative method disclosed includes, among other things, removing a portion of an initial gate cap layer and a portion of an initial sidewall spacer so as to thereby define a gate contact cavity that exposes a portion of a gate structure, completely forming a conductive gate contact structure (CB) in a gate contact cavity, wherein the entire conductive gate contact structure (CB) is positioned vertically above the active region. The method also comprises removing the remaining portion of the initial gate cap layer and to recess a vertical height of exposed portions of the initial sidewall spacer to thereby define a recessed sidewall spacer and a gate cap cavity and forming a replacement gate cap layer in the gate cap cavity so as to define an air space between an upper surface of the recessed sidewall spacer and a lower surface of the replacement gate cap layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: January 8, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chanro Park, Ruilong Xie, Hoon Kim, Min Gyu Sung
  • Patent number: 10163946
    Abstract: An image sensor may include a lower device that includes logic transistors, an intermediate device that is formed over the lower device and includes a Correlated Double Sampling (CDS) circuit and a capacitor, and an upper device that is formed over the intermediate device and includes a photodiode, a floating diffusion region, and a transfer gate electrode.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: December 25, 2018
    Assignee: SK Hynix Inc.
    Inventor: Young-Jun Kwon
  • Patent number: 10147823
    Abstract: A transistor with stable electrical characteristics. A semiconductor device that includes an oxide semiconductor, a first conductor, a first insulator, a second insulator, a third insulator, and a fourth insulator. The oxide semiconductor is positioned over the first insulator. The second insulator is positioned over the oxide semiconductor. The third insulator is positioned over the second insulator. The first conductor is positioned over the third insulator. The fourth insulator is positioned over the first conductor. The fourth insulator includes a region in contact with a top surface of the second insulator. The oxide semiconductor includes a region overlapping with the first conductor with the second insulator and the third insulator positioned therebetween. When seen from above, a periphery of the first insulator and a periphery of the second insulator are located outside a periphery of the oxide semiconductor.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: December 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10147656
    Abstract: A sizing device in a polishing apparatus for measuring a thickness of a wafer in course of polishing by laser beam interference, includes: a light-source for irradiating the wafer in course of polishing with a laser beam, a light-receiving portion for receiving reflected light from the wafer in course of polishing irradiated with the laser beam from the light-source, a calculating part for calculating a measured value of the thickness of the wafer in course of polishing irradiated with the laser beam based on the reflected light received through the light-receiving portion. The calculating part can calculate the wafer thickness in course of polishing by calculating a measuring error value of the wafer thickness in course of polishing from resistivity of the wafer in course of polishing based on a previously determined correlation between wafer resistivity and measuring error value of wafer thickness, and by compensating the measuring error value.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 4, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Shigeru Oba, Shiro Amagai
  • Patent number: 10128251
    Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: November 13, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Ting Li, Jen-Chieh Lin, Wen-Chin Lin, Po-Cheng Huang, Fu-Shou Tsai
  • Patent number: 10128310
    Abstract: According to one embodiment, a magnetoresistive memory device includes a magnetoresistive element of a stacked layer structure includes a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first and second magnetic layers, and an insulating layer of a group III-V compound provided on a side of the first magnetic layer of the magnetoresistive element, the insulating layer including an chemical element of group II, group IV, or group VI.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: November 13, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kuniaki Sugiura
  • Patent number: 10121779
    Abstract: Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a source and a drain defined within a body isolation well. A gate overlies the body isolation well between the source and the drain, and an isolating structure is formed within the body isolation well. The isolating structure sections the source into a plurality of source sections with the plurality of source sections adjacent to one gate.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: November 6, 2018
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Handoko Linewih, Chao Cheng
  • Patent number: 10121757
    Abstract: A pillar structure is disposed on a substrate. The pillar structure includes a pad, a metal wire bump, a metal wire, and a metal plating layer. The pad is disposed on the substrate. The metal wire bump is disposed on the pad. The metal wire is connected to the metal wire bump. The metal wire extends in a first extension direction, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction. The metal plating layer covers the pad and completely encapsulates the metal wire bump and the metal wire.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: November 6, 2018
    Assignee: Unimicron Technology Corp.
    Inventor: Cheng-Jui Chang
  • Patent number: 10109765
    Abstract: LED module chips are assembled by preparing red, green and blue LED substrates in regions partitioned at predetermined intervals. A module substrate has on its upper face a plurality of module chips each having an accommodation region for accommodating the red, green and blue LEDs therein. The front face of the LED substrate on which the LEDs are formed is opposed to the upper face of the module substrate. One of the LEDs is positioned to a predetermined one of the accommodation regions of the module chip, and a laser beam is irradiated from a rear face of the LED substrate to a buffer layer of LED with a condensing point of the laser beam positioned to the buffer layer to peel off the LED from an epitaxy substrate and accommodate the LED into the predetermined accommodation region of the module chip.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 23, 2018
    Assignee: DISCO Corporation
    Inventor: Kazuma Sekiya
  • Patent number: 10056303
    Abstract: A method of controlling NFET and PFET gate heights across different gate widths with chamfering and the resulting device are provided. Embodiments include forming an ILD over a fin; forming cavities in the ILD, each with similar or different widths; forming a high-K dielectric layer over the ILD and in each cavity; forming a pWF metal layer over the dielectric layer in one cavity; recessing the pWF metal layer to a height above the fin; forming an nWF metal layer in the cavities over the dielectric and pWF metal layers; recessing the nWF metal layer to a height above the pWF metal layer; forming a barrier layer over the dielectric and nWF metal layers; filling the cavities with a low-resistive metal; and recessing the barrier and dielectric layers to a height above the nWF metal layer; and concurrently etching the low-resistive metal.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Suraj Kumar Patil, Katsunori Onishi, Pei Liu, Chih-Chiang Chang
  • Patent number: 10029383
    Abstract: A hexagonal single crystal wafer is produced from a hexagonal single crystal ingot. The depth of the focal point of a laser beam is gradually changed from a shallow position not reaching the depth corresponding to the desired thickness of the wafer to a deep position corresponding to the desired thickness of the wafer in such a manner that a parabola is described by the path of the focal point. When the spot area of the laser beam on the upper surface of the ingot becomes a predetermined maximum value, the deep position of the focal point is maintained.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: July 24, 2018
    Assignee: DISCO CORPORATION
    Inventor: Kazuya Hirata
  • Patent number: 9972581
    Abstract: A package includes a first dielectric layer, a device die over and attached to the first dielectric layer, an active through-via and a dummy through-via, and an encapsulating material encapsulating the device die, the active through-via, and the dummy through-via. The package further includes a second dielectric layer over and contacting the device die, the active through-via, and the dummy through-via. An active metal cap is over and contacting the second dielectric layer and electrically coupling to the active through-via. The active metal cap overlaps the active through-via. A dummy metal cap is over and contacting the second dielectric layer. The dummy metal cap overlaps the dummy through-via. The dummy metal cap is separated into a first portion and a second portion by a gap. A redistribution line passes through the gap between the first portion and the second portion of the dummy metal cap.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: May 15, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, Meng-Tsan Lee, Tsung-Shu Lin, Wei-Cheng Wu, Chien-Chia Chiu, Chin-Te Wang
  • Patent number: 9893040
    Abstract: This application refers to a flip-chip structure of Group III semiconductor light emitting device. The flip-chip structure includes: a substrate, a buffer layer, nitride semiconductor layer, an active layer, a P type nitride semiconductor layer, a transparent conductive layer, a first insulation layer, a P type contact metal, a N type contact metal, a second insulation layer, a flip-chip P type electrode and a flip-chip N type electrode. The substrate, the buffer layer, the N type nitride semiconductor layer, the active layer, the P type nitride semiconductor layer which grow sequentially from bottom to top form a linear convex mesa. In this application, structure of the first insulation layer which is formed by aBraggs reflective layer, a metal layer and the multilayer oxide insulation layer, acts as a reflector structure and an insulation layer to replace the flip-chip reflector structure design and the first insulation layer, so that a metal protective layer can be omitted.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: February 13, 2018
    Assignee: XIANGNENG HUALEI OPTOELECTRONIC CO., LTD
    Inventor: Shuncheng Xu
  • Patent number: 9812605
    Abstract: In one example, a device includes a trench formed in a substrate. The trench includes a first end and a second end that are non-collinear. A first plurality of semiconductor pillars is positioned near the first end of the trench and includes integrated light sources. A second plurality of semiconductor pillars is positioned near the second end of the trench and includes integrated photodetectors.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: November 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Yann Astier, Huan Hu, Ning Li, Devendra K. Sadana, Joshua T. Smith, William T. Spratt
  • Patent number: 9779998
    Abstract: A method of manufacturing a semiconductor device is provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 3, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Chen Tsai, Hung-Chang Chang, Ta-Kang Lo, Tsai-Fu Chen, Shang-Jr Chen