Patents Examined by S. V. Clark
  • Patent number: 10777523
    Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Kenneth N. Hagen
  • Patent number: 10777511
    Abstract: A semiconductor device includes a semiconductor substrate, at least two first films, a bridge portion, and a conductive member. The two first films are spaced apart from each other, along a first direction which is an in-plane direction of the semiconductor substrate, and along a second direction which is in the in-plane direction of the semiconductor substrate and is perpendicular to the first direction. The bridge portion connects portions of side facing surfaces of the two first films to each other, and has a flat bottom surface. The conductive member is provided under the bottom surface of the bridge portion.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 15, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kazuhiro Ooshima
  • Patent number: 10767085
    Abstract: There is provided a semiconductor-bonding resin composition having excellent thermally conductive property and electrically conductive property and suitable for joining a power semiconductor element and an element support member. There are provided: a semiconductor-bonding resin composition containing (A) a bismaleimide resin including an aliphatic hydrocarbon group on a main chain, (B) a curing agent, (C) a filler containing electrically conductive particles having a specific gravity of 1.1 to 5.0, and (D) silver microparticles having an average particle size of 10 to 300 nm; a semiconductor-bonding sheet obtained using the semiconductor-bonding resin composition; and a semiconductor device including a semiconductor joined by the semiconductor-bonding sheet.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: September 8, 2020
    Assignee: KYOCERA CORPORATION
    Inventors: Masakazu Fujiwara, Hiroshi Fukukawa
  • Patent number: 10770383
    Abstract: A semiconductor device includes a plurality of semiconductor chips spaced apart from each other. A space region is formed between adjacent semiconductor chips of the plurality of semiconductor chips. A redistribution layer is disposed on at least one of the semiconductor chips. The redistribution layer includes at least one redistribution line electrically connected to the at least one of the semiconductor chip. The redistribution layer includes an interconnection disposed in the space region. The interconnection includes an organic layer disposed on the at least one redistribution line. The organic layer is more flexible than the plurality of semiconductor chips.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hohyeuk Im
  • Patent number: 10770367
    Abstract: A semiconductor apparatus includes: a substrate including a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the substrate; a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and a bonding agent bonding the case and the metal plate on a side face of the substrate.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Kitabayashi, Hiroshi Yoshida, Hidetoshi Ishibashi, Daisuke Murata
  • Patent number: 10763173
    Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: September 1, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shutesh Krishnan, Sw Wei Wang, Ch Chew, How Kiat Liew, Fui Fui Tan
  • Patent number: 10756022
    Abstract: Some embodiments include a semiconductor package. The semiconductor package has a semiconductor die with a primary region which includes integrated circuitry, and with an edge region which includes a portion of an alignment mark location. The portion of the alignment mark location includes a segment of an alignment mark. The alignment mark includes a pattern of lines and spaces, with the lines extending along a first direction. The portion of the alignment mark location also includes a texture having a pattern other than lines extending along either the first direction or along a second direction substantially orthogonal to the first direction. Some embodiments include methods for alignment marking semiconductor wafers.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Richard T. Housley, Jianming Zhou
  • Patent number: 10755995
    Abstract: A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Ting Wang, Yi-An Lin, Ching-Chuan Chang, Po-Chang Kuo
  • Patent number: 10756001
    Abstract: Provided is a semiconductor module comprising: a semiconductor chip; a cooling portion having a refrigerant passing portion through which a refrigerant passes; and a laminated substrate having: a first metal interconnection layer; a second metal interconnection layer; and an insulation provided between the first metal interconnection layer and the second metal interconnection layer, wherein the cooling portion has: a top plate; a bottom plate; and a plurality of protruding parts which are provided on a surface of the bottom plate, and are separated from each other in a flow direction of the refrigerant, and are respectively provided continuously in a direction orthogonal to the flow direction, wherein the plurality of protruding parts are provided at a position overlapping with one end of the second metal interconnection layer and at a position overlapping with the semiconductor chip in the flow direction.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 25, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akio Kitamura, Shinichiro Adachi, Nobuhide Arai
  • Patent number: 10756126
    Abstract: The present application provides a flexible display panel and a manufacturing method thereof. The flexible display panel includes a flexible substrate, a buffer layer formed on the flexible substrate, and a metal layer formed on the buffer layer. The flexible display panel includes a display area and a bending area in a lateral direction. The buffer layer includes a first portion and a second portion, the first portion corresponding to the display area, the second portion corresponding to the bending area, and the thickness of the second portion is less than the thickness of the first portion.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: August 25, 2020
    Assignee: Kunshan New Flat Panel Display Technology Center Co., Ltd.
    Inventors: Bo Yuan, Genmao Huang, Zhiyuan Cui, Kun Hu, Lin Xu, Bo Li
  • Patent number: 10755998
    Abstract: A metal member includes a metal substrate and a porous metal layer. A composite includes the metal member and a resin member. The metal substrate has one surface, is made of a metal material, and has a region formed as an uneven layer having an uneven shape with respect to the one surface. The porous metal layer has a mesh-like shape and is formed on the uneven layer. The uneven layer includes a plurality of protrusions protruding in a direction normal to the one surface.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: August 25, 2020
    Assignee: DENSO CORPORATION
    Inventors: Takumi Nomura, Wataru Kobayashi, Kazuki Koda
  • Patent number: 10748786
    Abstract: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: August 18, 2020
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Ronald Patrick Huemoeller, Michael G. Kelly, Curtis Zwenger
  • Patent number: 10741475
    Abstract: A delivery roll (1) for thermal interface components, the roll comprising a carrier tape (10), an adhesive layer (10a), and a plurality of thermal interface components (20), wherein the adhesive layer (10a) is arranged on a surface of the carrier tape (10); each thermal interface component (20) comprises a top liner (22), a bottom liner (26) and a thermal interface pad (24) arranged therebetween; the carrier tape (10) supports the plurality of thermal interface components (20) by the adhesive adhering to the bottom liner (26) of each thermal interface component (20); and the plurality of thermal interface components (20) is arranged in a spaced apart manner along the carrier tape (10). The invention also relates to a manufacturing method for a delivery roll.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: August 11, 2020
    Assignee: NOLATO SILIKONTEKNIK AB
    Inventors: Xiongwei Lu, Mark D. Kittel, Jussi Myllyluoma
  • Patent number: 10741503
    Abstract: Provided herein are conductive formulations wherein graphene has been added into the metal system, thereby reducing curing shrinkage and improving flexibility, without significantly affecting the EMI shielding performance thereof. In accordance with certain aspects of the present invention, there are also provided methods for filling a gap in an electronic package to achieve electromagnetic interference (EMI) shielding thereof, as well as the resulting articles shielded thereby. In certain aspects of the present invention, there are also provided articles prepared using invention formulations and methods.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: August 11, 2020
    Assignee: HENKEL IP & HOLDING GMBH
    Inventors: Xuan Hong, Juliet G. Sanchez, Xinpei Cao, Qizhuo Zhuo
  • Patent number: 10741485
    Abstract: A nanostructure energy storage device comprising: at least a first plurality of conductive nanostructures provided on an electrically insulating surface portion of a substrate; a conduction controlling material embedding each nanostructure in said first plurality of conductive nanostructures; a first electrode connected to each nanostructure in said first plurality of nanostructures; and a second electrode separated from each nanostructure in said first plurality of nanostructures by said conduction controlling material, wherein said first electrode and said second electrode are configured to allow electrical connection of said nanostructure energy storage device to an integrated circuit.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 11, 2020
    Assignee: SMOLTEK AB
    Inventors: M Shafiqul Kabir, Anders Johansson, Muhammad Amin Saleem, Peter Enoksson, Vincent Desmaris, Rickard Andersson
  • Patent number: 10741463
    Abstract: A module 1a includes a multilayer wiring board 2, a component 3 that is mounted on a main surface 2a of the multilayer wiring board 2, a sealing-resin layer 4 that is laminated on the main surface 2a of the multilayer wiring board 2, and a resin coating layer 7 that coats a surface of the sealing-resin layer 4. The resin coating layer 7 includes a shield film 5 and outer electrodes 6, and opposite surfaces 6a of the outer electrodes 6 and an opposite surface 5a of the shield film 5 are formed on the same plane. The module 1a can be connected to, for example, an external antenna without using a wiring electrode of a mother substrate, and thus, signal loss can be suppressed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: August 11, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Shigeru Endo
  • Patent number: 10730743
    Abstract: A gas sensor package is disclosed. The gas sensor package can include a housing defining a first chamber and a second chamber. An electrolyte can be provided in the first chamber. A gas inlet can provide fluid communication between the second chamber and the outside environs. The gas inlet can be configured to permit gas to enter the second chamber from the outside environs. An integrated device die can be mounted to the housing. The integrated device die can comprise a sensing element configured to detect the gas. The integrated device die can have a first side exposed to the first chamber and a second side exposed to the second chamber, with the first side opposite the second side.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: August 4, 2020
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Oliver J. Kierse, Rigan McGeehan, Alfonso Berduque, Donal Peter McAuliffe, Raymond J. Speer, Brendan Cawley, Brian J. Coffey, Gerald Blaney
  • Patent number: 10734358
    Abstract: Processes for configuring a plurality of independent die packages for socketing. The packages are attached to a carrier wafer with a release film. The attached plurality of independent die packages are overmolded to provide a molded multi-die package. The molded multi-die package is planarized to expose the dies, singulated, and released from the carrier wafer. The singulated, molded multi-die packaging may be picked for further processing and placed into a socket. A plurality of molded, multi-die packages may be placed in a socket and operate as a computer system. The independent die packages may each perform and same computer application function or different computer application functions, and may have the same or different dimensions. The socket may have any of a number of configurations as may be needed.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Jonathan L. Rosch, Amruthavalli Pallavi Alur, Arun Chandrasekhar, Shawna M. Liff
  • Patent number: 10734333
    Abstract: Semiconductor packages including a lateral interconnect having an arc segment to increase self-inductance of a signal line is described. In an example, the lateral interconnect includes a circular segment extending around an interconnect pad. The circular segment may extend around a vertical axis of a vertical interconnect to introduce an inductive circuitry to compensate for an impedance mismatch of the vertical interconnect.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Khang Choong Yong, Howard Lincoln Heck
  • Patent number: 10734313
    Abstract: A semiconductor package includes a leadframe and a semiconductor die attached to the leadframe by way of solder posts. In a stacked arrangement, the package also includes a passive component disposed between the leadframe and the semiconductor die and electrically connected to the semiconductor die through the leadframe.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: August 4, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Morroni, Rajeev Dinkar Joshi, Sreenivasan K. Koduri, Sujan Kundapur Manohar, Yogesh K. Ramadass, Anindya Poddar