Patents Examined by S. V. Clark
  • Patent number: 11037852
    Abstract: A package includes a substrate having a conductive layer, and the conductive layer comprises an exposed portion. A die stack is disposed over the substrate and electrically connected to the conductive layer. A high thermal conductivity material is disposed over the substrate and contacting the exposed portion of the conductive layer. The package further includes a contour ring over and contacting the high thermal conductivity material.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wensen Hung, Szu-Po Huang, Hsiang-Fan Lee, Kim Hong Chen, Chi-Hsi Wu, Shin-Puu Jeng
  • Patent number: 11031353
    Abstract: A microelectronic device and/or microelectronic device package having a warpage control structure. The warpage control structure may be positioned over an encapsulating material, wherein the encapsulating material is positioned between the warpage control structure and a die positioned over a substrate. The warpage control structure may have a first thickness over a first portion of the encapsulating material and a second thickness over a second portion of the encapsulating material. Methods of forming the microelectronic device are also disclosed herein.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher Glancey, Shams U. Arifeen
  • Patent number: 11031256
    Abstract: A semiconductor device having one or more tiered pillars and methods of manufacturing such a semiconductor device are disclosed. The semiconductor device may include redistribution layers, a semiconductor die, and a plurality of interconnection structures that operatively couple a bottom surface of the semiconductor die to the redistribution layers. The semiconductor device may further include one or more conductive pillars about a periphery of the semiconductor die. The one or more conductive pillars may be electrically connected to the redistribution layers and may each comprise a plurality of stacked tiers.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 8, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Ronald Patrick Huemoeller, Michael G. Kelly, Curtis Zwenger
  • Patent number: 11031370
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method for manufacturing a semiconductor device that comprises ordering and performing processing steps in a manner that prevents warpage deformation from occurring to a wafer and/or die due to mismatching thermal coefficients.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: June 8, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Yeong Beom Ko, Jin Han Kim, Dong Jin Kim, Do Hyung Kim, Glenn Rinne
  • Patent number: 11032629
    Abstract: A microelectromechanical microphone includes: a substrate; a sensor chip, integrating a microelectromechanical electroacoustic transducer; and a control chip operatively coupled to the sensor chip. In one embodiment, the sensor chip and the control chip are bonded to the substrate, and the sensor chip overlies, or at least partially overlies, the control chip. In another embodiment, the sensor is bonded to the substrate and a barrier is located around at least a portion of the sensor chip.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 8, 2021
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS (MALTA) LTD
    Inventors: Roberto Brioschi, Paul Anthony Barbara
  • Patent number: 11018098
    Abstract: A system may include a first semiconductor substrate having a first side and a second side opposite the first side. The system may further include multiple device layers positioned on the first side of the substrate. The system may also include a first portion of an antenna structure positioned within at least one of the multiple device layers. The system may include a second portion of the antenna structure positioned over the second side of the substrate. The system may further include a via passing through the substrate and electrically coupling the first portion of the antenna structure to the second portion of the antenna structure.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John F. Kaeding, Owen R. Fay
  • Patent number: 11011494
    Abstract: Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 18, 2021
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Guilian Gao, Gaius Gillman Fountain, Jr., Laura Wills Mirkarimi, Rajesh Katkar, Ilyas Mohammed, Cyprian Emeka Uzoh
  • Patent number: 11011503
    Abstract: Direct-bonded optoelectronic interconnects for high-density integrated photonics are provided. A combined electrical and optical interconnect enables direct-bonding of fully-processed optoelectronic dies or wafers to wafers with optoelectronic driver circuitry. The photonic devices may be III-V semiconductor devices. Direct-bonding to silicon or silicon-on-insulator (SOI) wafers enables the integration of photonics with high-density CMOS and other microelectronics packages. Each bonding surface has an optical window to be coupled by direct-bonding. Coplanar electrical contacts lie to the outside, or may circumscribe the respective optical windows and are also direct-bonded across the interface using metal-to-metal direct-bonding, without interfering with the optical windows. Direct hybrid bonding can accomplish both optical and electrical bonding in one overall operation, to mass-produce mLED video displays.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 18, 2021
    Assignee: INVENSAS BONDING TECHNOLOGIES, INC.
    Inventors: Liang Wang, Rajesh Katkar
  • Patent number: 11011454
    Abstract: A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device comprising a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 18, 2021
    Assignee: ROHM CO., LTD.
    Inventors: Katsuhiko Yoshihara, Masao Saito
  • Patent number: 10998249
    Abstract: A semiconductor assembly includes a semiconductor element having contacts on a first surface electrically connected with contacts of a carrier element by electrically conductive material. A second surface opposite the first surface has a convex curvature with a first radius or a concave curvature with a second radius. The second surface of the convex curvature or the second surface of the concave curvature is connected in a positive-fit manner to a cooling body surface of a concave cooling body curvature of the cooling body, and, during operation at a selected barrier layer temperature, the first radius of the convex curvature deviates by at most 10% from a third radius of the concave cooling body curvature, or the second radius of the concave curvature deviates by at most 10% from a fourth radius of the convex cooling body curvature.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: May 4, 2021
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Stefan Pfefferlein, Thomas Bigl, Ewgenij Ochs
  • Patent number: 10991663
    Abstract: A method is disclosed and includes forming a plurality of dummy conductive cells that provides different densities in empty areas in metal layers of a semiconductor device according to overlap conditions of the empty areas each arranged between a pair of neighboring metal layers of metal layers. Forming the plurality of dummy conductive cells includes operations of forming a group of dummy conductive cells in a single empty area of the empty areas when the single empty area in one pair of the neighboring metal layers is overlapped by a signal line in the same pair of the neighboring metal layers. When viewed in plan view, projection areas of the group of dummy conductive cells are vertically overlapped by a projection area of the signal line. A semiconductor device is also disclosed herein.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Yu Ma, Hui-Mei Chou, Kuo-Ji Chen
  • Patent number: 10991599
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Paul A. Nyhus
  • Patent number: 10985136
    Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate, wherein the microelectronic die stack may include a first microelectronic die having an active surface and an opposing back surface, a first side and an opposing second side, wherein the first microelectronic die may include a plurality of primary bond pads on the active surface proximate the first side and at least one secondary bond pad on the active surface proximate the second side. The microelectronic die stack may further include a second microelectronic die having an active surface and an opposing back surface, wherein the back surface of the second microelectronic die is attached to the active surface of the first microelectronic die and wherein the second microelectronic die is rotated relative to the first microelectronic die to expose the at least one secondary bond pad of the first microelectronic die.
    Type: Grant
    Filed: December 11, 2016
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventor: Sheldon Hiemstra
  • Patent number: 10978342
    Abstract: The present invention provides interconnects with self-forming wrap-all-around graphene barrier layer. In one aspect, a method of forming an interconnect structure is provided. The method includes: patterning at least one trench in a dielectric; forming an interconnect in the at least one trench embedded in the dielectric; and forming a wrap-all-around graphene barrier surrounding the interconnect. An interconnect structure having a wrap-all-around graphene barrier is also provided.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 13, 2021
    Assignee: International Business Machines Corporation
    Inventors: Huai Huang, Takeshi Nogami, Alfred Grill, Benjamin D. Briggs, Nicholas A. Lanzillo, Christian Lavoie, Devika Sil, Prasad Bhosale, James Kelly
  • Patent number: 10978405
    Abstract: An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 10978378
    Abstract: A leadless package includes an at least partially electrically conductive carrier having a mounting section and a lead section, an electronic chip mounted on the mounting section, and an encapsulant at least partially encapsulating the electronic chip and partially encapsulating the carrier so that at least part of an interior sidewall of the lead section not forming part of an exterior sidewall of the package is exposed.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 13, 2021
    Assignee: Infineon Technologies AG
    Inventors: Thomas Bemmerl, Kuok Wai Chan, Christoph Liebl, Bun Kian Tay, Wee Boon Tay, Wae Chet Yong
  • Patent number: 10971474
    Abstract: A chip package and method of fabricating the same are described herein. The chip package generally includes a stand-off which spaces a die from a substrate to control the collapse of a solder joint coupling the die to the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 6, 2021
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Henley Liu
  • Patent number: 10950577
    Abstract: An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 10930617
    Abstract: The present disclosure provides a wafer-level system-in-package (WLSiP) packaging method and a WLSiP package structure. The WLSiP package structure includes a device substrate including a substrate and a plurality of first chips on the substrate, an encapsulation layer, covering the device substrate, a plurality of second chips embedded in the encapsulation; and an electrical connection structure, electrically connecting at least one of the plurality of second chips with at least one of the plurality of first chips. The plurality of first chips and the plurality of second chips are staggered from each other.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: February 23, 2021
    Assignee: Ningbo Semiconductor International Corporation
    Inventor: Mengbin Liu
  • Patent number: 10923413
    Abstract: Hard IP blocks, such as SerDes chips, are designed with keepout zones beneath the surface interconnects, the keepout zones being spaces within the chip where there is no circuitry. Connections can be formed between surface interconnects on an under surface of the SerDes chip that faces the host die, and surface interconnects on an upper surface of the SerDes chip that interfaces without external devices. Accordingly, redistribution layers routing around an outer periphery of the SerDes chip are no longer needed, and the resistive capacitive load remains low so as not to adversely impact transmitted signals.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 16, 2021
    Assignee: Xcelsis Corporation
    Inventor: Javier A. Delacruz