Abstract: Techniques regarding one or more VFETs operably coupled to bottom contacts with low electrical resistance are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a vertical field-effect transistor device that can comprise a semiconductor fin positioned on a source/drain region, which can comprise a semiconductor substrate. The apparatus can also comprise a metal contact layer positioned on the source/drain region and at least partially surrounding a base of the semiconductor fin. Further, the metal contact layer can be in electrical communication with the source/drain region.
November 7, 2018
Date of Patent:
October 19, 2021
INTERNATIONAL BUSINESS MACHINES CORPORATION
Chen Zhang, Tenko Yamashita, Terence B Hook, Brent Alan Anderson
Abstract: In a semiconductor device including a nonvolatile memory, information of a memory transistor of an unselected bit is accidentally erased during information write operation. A well region is provided in a memory region of a bulk region defined in a SOI substrate. A memory transistor having an LDD region and a diffusion layer is provided in the well region. A raised epitaxial layer is provided on the surface of the well region. The LDD region is provided from a portion of the well region located directly below a sidewall surface of a gate electrode to a portion of the well region located directly below the raised epitaxial layer. The diffusion layer is provided in the raised epitaxial layer.
Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.
Abstract: One illustrative method of forming heterojunction bipolar devices includes, among other things, forming a first gate structure above an active semiconductor layer, forming a second gate structure adjacent a first side of the first gate structure, forming a third gate structure adjacent a second side of the first gate structure, forming an emitter of a bipolar transistor in the active semiconductor layer between the first gate structure and the second gate structure, forming a collector of the bipolar transistor in the active semiconductor layer between the first gate structure and the third gate structure, and forming a first base contact contacting the active region adjacent an end of the first gate structure, wherein a portion of the active semiconductor layer positioned under the first gate structure defines a base of the bipolar transistor.
Abstract: A semiconductor device has a semiconductor substrate that includes an element range and a peripheral range. The semiconductor substrate includes: a body region disposed within the element range; a p-type deep region that is disposed from the element range through the peripheral range, is distributed from an upper surface of the semiconductor substrate to a position deeper than a lower end of each gate trench, and involves end gate trench; and a p-type voltage resistance region that is disposed within the peripheral range, and is distributed from the upper surface to a position shallower than a lower end of the p-type deep region. A p-type impurity concentration within the p-type deep region is increased in the direction from the body region toward the p-type voltage resistance region.
Abstract: A semiconductor device includes: a wire including a first conductive member disposed at a semiconductor substrate and a second conductive member disposed at a surface of the first conductive member, the second conductive member having an ionization tendency less than the first conductive member, wherein the first conductive member includes a first surface disposed close to the second conductive member and having a width smaller than a width of a second surface of the first conductive member which is disposed close to the semiconductor substrate, and wherein the second conductive member has a width larger than the width of the first surface of the first conductive member and smaller than the width of the second surface of the first conductive member.
Abstract: Various embodiments of the present application are directed towards a control gate layout to improve an etch process window for word lines. In some embodiments, an integrated chip comprises a memory array, an erase gate, a word line, and a control gate. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The erase gate and the word line are elongated in parallel along a row of the memory array. The control gate is elongated along the row and is between and borders the erase gate and the word line. Further, the control gate has a pad region protruding towards the erase gate and the word line. Because the pad region protrudes towards the erase gate and the word line, a width of the pad region is spread between word-line and erase-gate sides of the control gate.
Abstract: A semiconductor device includes a first conductivity type semiconductor layer including an active cell portion and an outer peripheral portion around the active cell portion, a second conductivity type body region selectively formed at a surface portion of the semiconductor layer in the active cell portion, a first conductivity type source region formed at an inner part of the body region, a gate electrode that faces a part of the body region through a gate insulating film, a second conductivity type column layer straddling a boundary between the active cell portion and the outer peripheral portion inside the semiconductor layer such that the column layer is disposed at a lower part of the body region in the active cell portion, a source electrode that is electrically connected to the source region, and an outer peripheral electrode that is electrically connected to the column layer in the outer peripheral portion.
Abstract: Disclosed are a pixel element, a method for fabricating same, a display control method, a display panel. The pixel element includes a base substrate, display and non-display areas on the base substrate, a control electrode, an adjustment layer, a transparent electrode in the non-display area, the transparent electrode and the adjustment layer are arranged in a stack, the control electrode is at the interface between display and non-display areas, and surrounds the adjustment layer, and there is a gap area between the control electrode and the adjustment layer; and the adjustment layer includes charged particles configured to move to the control electrode and the transparent electrode under control of first and second electric fields, the first and second electric fields are created after signals are applied to the control electrode and the transparent electrode, and direction of the first electric field is opposite to direction of the second electric field.
Abstract: The disclosure is directed to spin-orbit torque (“SOT”) magnetoresistive random-access memory (“MRAM”) (“SOT-MRAM”) structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.
Abstract: A semiconductor structure is provided. The semiconductor structure includes a shallow trench isolation (STI) region on a well region of a substrate, a plurality of transistors, and a power rail. Each of the transistors includes at least one fin, a gate electrode formed on the fin, and a doping region formed on the fin. The fin is formed on the well region, and is extending in a first direction. The gate electrode is extending in a second direction that is perpendicular to the first direction. The power rail is formed in the STI region and below the doping regions of the transistors, and extending in the first direction. Each of the doping regions is electrically connected to the power rail, so as to form a source region of the respective transistor. The power rail is electrically connected to the well region of the substrate.
Abstract: A crystal of a group 13 nitride has an upper surface and lower surface and is composed of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride or the mixed crystals thereof. When the upper surface of the layer of the crystal of the group 13 nitride is observed by cathode luminescence, the upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part. A half value width of reflection at the (0002) plane of a X-ray rocking curve on the upper surface is 3000 seconds or less and 20 seconds or more.
Abstract: A TFT substrate includes a plurality of antenna element regions each including a TFT and a patch electrode electrically connected to a drain electrode of the TFT. The TFT substrate further includes a source metal layer including a source electrode of the TFT, a gate metal layer formed on the source metal layer and including a gate electrode of the TFT, a semiconductor layer of the TFT, a gate insulating layer formed between the semiconductor layer and the gate metal layer, wherein the source metal layer further includes the patch electrode. The TFT substrate further includes a source terminal portion arranged in a non-transmitting/receiving region, and the gate metal layer further includes a source terminal upper connection portion of the source terminal portion.
Abstract: A TFT and a method for manufacturing the TFT, an array substrate, and a display device are provided. An active layer of the TFT includes a channel region, a first conductive region and a second conductive region, and the channel region is arranged between the first conductive region and the second conductive region. The channel region includes a first side and a second side, the first side is opposite to the second side, the first side is in contact with a third side of the first conductive region, the second side is in contact with a fourth side of the second conductive region, and a length of the first side is greater than a length of the third side.
Abstract: An electronic device including a two-dimensional electron gas is provided. The electronic device includes a substrate, a first material layer disposed on the substrate and formed of a binary oxide, a second material layer disposed on the first material layer and formed of a binary oxide, and a two-dimensional electron gas generated between the first material layer and the second material layer.
September 24, 2015
Date of Patent:
August 3, 2021
INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS
Abstract: A light emitting device includes a light emitting element including a first base member, and a stacked body provided to the first base member, and a second base member provided with the light emitting element, the stacked body includes a first columnar section having a first height, and a second columnar section having a second height smaller than the first height, the first columnar section and the second base member are electrically connected to each other via a first conductive member between the stacked body and the second base member, the second columnar section and the second base member are electrically connected to each other via a second conductive member between the stacked body and the second base member, the first conductive member has a third height, and the second conductive member has a fourth height larger than the third height.
Abstract: An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N? drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET.
June 4, 2019
Date of Patent:
July 27, 2021
GeneSIC Semiconductor Inc.
Siddarth Sundaresan, Ranbir Singh, Jaehoon Park
Abstract: A pressure sensor device includes a semiconductor die of the pressure sensor device and a bond wire of the pressure sensor device. A maximal vertical distance between a part of the bond wire and the semiconductor die is larger than a minimal vertical distance between the semiconductor die and a surface of a gel covering the semiconductor die.
October 15, 2018
Date of Patent:
July 20, 2021
Emanuel Stoicescu, Matthias Boehm, Stefan Jahn, Erhard Landgraf, Michael Weber, Janis Weidenauer
Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.
Abstract: The present invention discloses a Micro-Electro-Mechanical System (MEMS) acoustic pressure sensor device and a method for making same. The MEMS device includes: a substrate; a fixed electrode provided on the substrate; and a multilayer structure, which includes multiple metal layers and multiple metal plugs, wherein the multiple metal layers are connected by the multiple metal plugs. A cavity is formed between the multilayer structure and the fixed electrode. Each metal layer in the multilayer structure includes multiple metal sections. The multiple metal sections of one metal layer and those of at least another metal layer are staggered to form a substantially blanket surface as viewed from a moving direction of an acoustic wave.