Abstract: This disclosure pertains to the field of nanotechnology. The disclosure provides methods of preparing nanostructures using a Group IV metal halide. The nanostructures have high quantum yield, narrow emission peak width, tunable emission wavelength, and colloidal stability. Also provided are nanostructures prepared using the methods. And, nanostructure films and molded articles comprising the nanostructures are also provided.

Abstract: Provided is a joint structure. The joint structure includes a first structure, and a second structure joined to the first structure via a joint portion formed of a Au—Sn-based alloy, wherein a thickness of the joint portion is 3 ?m or more and 50 ?m or less.

Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a substrate and a fin protruding from the substrate in a first direction. In addition, the fin includes a well region and an anti-punch through region over the well region. The semiconductor structure further includes a barrier layer formed over the anti-punch through region and channel layers formed over the fin and spaced apart from the barrier layer in the first direction. The semiconductor structure further includes a first liner layer formed around the fin and an isolation structure formed over the first liner layer. The semiconductor structure further includes a gate wrapping around the channel layers and extending in a second direction. In addition, a top surface of the barrier layer is higher than a top surface of the first liner layer in a cross-sectional view along the second direction.

Abstract: Methods are disclosed herein for forming fin-like field effect transistors (FinFETs) that maximize strain in channel regions of the FinFETs. An exemplary method includes forming a fin having a first width over a substrate. The fin includes a first semiconductor material, a second semiconductor material disposed over the first semiconductor material, and a third semiconductor material disposed over the second semiconductor material. A portion of the second semiconductor material is oxidized, thereby forming a second semiconductor oxide material. The third semiconductor material is trimmed to reduce a width of the third semiconductor material from the first width to a second width. The method further includes forming an isolation feature adjacent to the fin. The method further includes forming a gate structure over a portion of the fin, such that the gate structure is disposed between source/drain regions of the fin.

Abstract: An electronic component and a manufacturing method thereof are provided. The electronic component includes a structure member and a connecting member. The structure member includes at least one working unit. The at least one working unit is disposed in a first region. The connecting member is disposed on the structure member and includes a second region. The second region is overlapped with the first region, and a metal density of the second region is less than a metal density of the first region. The electronic component and the manufacturing method thereof of the embodiment of the disclosure include the effect of improving the reliability or quality of the electronic component.

Abstract: The invention relates to a power electronics module including a first circuit carrier (5,10, 11), as well as an electronic assembly (20, 30) arranged in an electrically contacting manner on the upper flat side of the first circuit carrier (5, 10, 11), and a first cooling element (40) in thermal contact with the underside of the first circuit carrier (5, 10, 11), wherein the module has at least one second assembly (20, 30) arranged on the upper side of a second circuit carrier (5, 10, 11) and a second cooling element (40) arranged on the underside of the second circuit carrier (5, 10, 11), wherein the first and the second circuit carriers (5, 10, 11) are arranged with their upper sides facing one another and at least one central heat sink (60, 61, 63, 64) that is electrically insulated from the assemblies (20, 30) is arranged in the space between the assemblies (20, 30), wherein the assemblies (20, 30) and the at least one central heat sink (60, 61, 63, 64) are embedded in a heat-conducting potting compound (5

Abstract: In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.

Abstract: A method of forming an integrated circuit structure includes forming a first magnetic layer, forming a first conductive line over the first magnetic layer, and coating a photo-sensitive coating on the first magnetic layer. The photo-sensitive coating includes a first portion directly over the first conductive line, and a second portion offset from the first conductive line. The first portion is joined to the second portion. The method further includes performing a first light-exposure on the first portion of the photo-sensitive coating, performing a second light-exposure on both the first portion and the second portion of the photo-sensitive coating, developing the photo-sensitive coating, and forming a second magnetic layer over the photo-sensitive coating.

Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device) and a method of making the same. A floating island of a second conductivity type of a cell region, a floating island of the second conductivity type of a termination region, a pillar of the second conductivity type of the cell region and a pillar of the second conductivity type of the termination region may be formed through adding a super junction mask (or reticle) after forming the epitaxial layer of a first conductivity type, through a well mask (or reticle) before or after forming a well of the second conductivity type, and through a contact mask (or reticle) before or after forming a contact structure. Therefore, the process is simple, the cost is low and yield and reliability are high.

Abstract: A device including a first layer, a MEMS component and/or an ASIC component on the first layer, and a second layer having a cavity receiving the MEMS component and/or the ASIC component. The second layer has a feedthrough for transmission of at least one of an electrical signal, an electromagnetic signal, a fluid, and a force.

Abstract: Technologies are provided for microelectromechanical microphones that can be robust to substantial pressure changes in the environment in which the micromechanical microphones operate. In some embodiments, a microelectromechanical microphone device can include a rigid plate defining multiple openings that permit passage of a pressure wave. The microelectromechanical microphone device also includes a stiffener member integrated into the rigid plate. The stiffener member causes stress to be distributed within the rigid plate in response to the pressure wave inducing deformation of the rigid plate.

Abstract: A method of manufacturing a light emitting device includes: providing a light emitting element comprising: a semiconductor laminate having a first surface, a second surface, and a lateral surface between the first and second surfaces, and an electrode disposed at the second surface; disposing a resin layer in an A-stage state on a support; placing the light emitting element on an upper surface of the resin layer while the upper surface of the resin layer and the first surface of the semiconductor laminate face each other; heating the resin layer at a first temperature to reduce a viscosity of the resin layer and causing the light emitting element to sink due to its own weight such that the second surface of the semiconductor laminate is exposed; and curing the resin layer by heating the resin layer at a second temperature higher than the first temperature, thereby forming a resin member.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes a stack and a plurality of memory strings. The stack is disposed on the substrate, and the stack includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. The memory strings pass through the stack along a first direction, wherein a first memory string in the memory strings includes a first conductive pillar and a second conductive pillar, a channel layer, and a memory structure. The first conductive pillar and the second conductive pillar respectively extend along the first direction and are separated from each other. The channel layer is disposed between the first conductive pillar and the second conductive pillar. The memory structure surrounds the second conductive pillar, and the memory structure includes a resistive memory material.

Abstract: A display apparatus including a substrate, and pixel regions and at least one separation region between the pixel regions, each pixel region including a first LED stack, a second LED stack adjacent to the first LED stack, a third LED stack adjacent to the second LED stack and each having a side surface forming a first angle, a second angle, and a third angle with the substrate, respectively, electrode pads electrically connected to the first, second, and third LED stacks, and an insulation layer disposed on at least one of the first, second, and third LED stacks, in which the first LED stack is configured to emit light having a longer peak wavelength than that emitted from the second and third LED stacks, and the first angle is different from the second and third angles.

Abstract: A semiconductor device includes an oxide semiconductor film having a corundum structure or containing as a major component gallium oxide or a mixed crystal of gallium oxide, and the semiconductor device is a normally-off semiconductor device with a threshold voltage that is 3V or more.

Abstract: Various methods and various staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.

Abstract: A method for manufacturing a memory device includes: a substrate is provided, the substrate including active regions; Bit Lines (BLs) are formed over the substrate, the BLs covering part of the active regions; a supporting layer is formed over the substrate covering the BLs and the substrate, first middle holes penetrating through the supporting layer and extending to the active regions are formed on the supporting layer, and gaps are formed between the first middle holes and the BLs; first protective layers are formed in the first middle holes, and etching holes which communicate with the substrate are formed in the first protective layers; the substrate and the active regions exposed in the etching holes are etched along the etching holes to form contact grooves; guide wires electrically connecting the active regions are formed in the first middle holes, the etching holes and the contact groove.

Abstract: A chip manufacturing method includes a modified layer forming step of forming a modified layer and a crack by applying, along planned dividing lines, a first laser beam having a wavelength transmitted through a substrate of a wafer including the substrate and a laminate in a state in which the back surface side of the substrate is exposed and a condensing point of the first laser beam is positioned within the substrate from the back surface side of the substrate, a grinding step of thinning the wafer to a predetermined thickness by grinding the back surface side of the substrate exposed in the modified layer forming step, and a laser-processed groove forming step of forming a laser-processed groove in the laminate by applying, along the planned dividing lines, a second laser beam having a wavelength absorbed by the substrate, from the front surface side of the wafer.

Abstract: A manufacturing method of an interconnect structure including the following is provided. A substrate is provided. Sacrificial layers are formed on the substrate. A dielectric layer is formed between two adjacent sacrificial layers. There is an air gap in the dielectric layer. The sacrificial layers are removed to form first openings. A conductive layer is formed in the first opening.

Abstract: A semiconductor device includes: a semiconductor layer; first and second transistors; one or more first source pads and a first gate pad of the first transistor in a first region of the upper surface of the semiconductor layer; and one or more second source pads and a second gate pad of the second transistor in a second region of the upper surface adjacent to the first region in a plan view of the semiconductor layer. In a plan view of the semiconductor layer, a virtual straight line connecting the centers of the first and second gate pads passes through the center of the semiconductor layer and forms a 45 degree angle with each side of the semiconductor layer. An upper surface boundary line between the first and second regions monotonically changes in the directions of extension of the longer and shorter sides of the semiconductor layer.