Patents Examined by Samuel A Gebremariam
  • Patent number: 10818626
    Abstract: Provided is connection wiring capable of inhibiting connection defects between bumps and pads at the time of semiconductor chip mounting and also allowing an increase in the number of pads. In an area between a pad row in any stage and a pad row in an adjacent stage, a first line 31 is disposed so as to pass under an adjacent second line 32, or a second line 32 is disposed so as to pass over an adjacent first line 31. In this case, three lines are disposed in any area between pads 20 in each stage such that the three lines include a first line 31 situated in the middle, and second lines 32 are situated so as to have the first line 31 positioned therebetween. Thus, the pitch between the pads 20 can be further reduced without reducing the width of the pads 20.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: October 27, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Seiji Muraoka, Yukio Shimizu, Motoji Shiota
  • Patent number: 10811578
    Abstract: A LED carrier includes a substrate, a conductive layer, an adhesive layer, and a reflector. The conductive layer is disposed on the substrate, and has a bonding portion and an extending portion. The bonding portion has a top surface higher than a top surface of the extending portion. The adhesive layer covers the extending portion of the conductive layer and exposes the bonding portion of the conductive layer. The reflector is disposed over the adhesive layer. The adhesive layer has a hook portion in contact with a corner of the reflector.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 20, 2020
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventors: Chih-Hao Lin, Chun-Peng Lin, Chang-Han Chen, Kuang-Neng Yang, Cheng-Ta Kuo
  • Patent number: 10804300
    Abstract: A complementary thin film transistor drive back-plate and manufacturing method thereof, a display panel.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: October 13, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Jang Soon Im
  • Patent number: 10804434
    Abstract: A nitride semiconductor light emitting element configured to emit deep ultraviolet light, the light emitting element comprises: an n-side contact layer comprising Al, Ga, and N; and an n-electrode disposed on the contact layer, wherein the n-electrode comprises, successively from the n-side contact layer side, a first layer consisting essentially of Ti, a second layer consisting essentially of a Si-containing Al alloy, and a third layer comprising at least one of a layer consisting essentially of Ta and/or a layer consisting essentially of W.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 13, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Takumi Otsuka
  • Patent number: 10797044
    Abstract: An electrostatic discharge (ESD) protection device includes a semiconductor substrate and a semiconductor fin located on the semiconductor substrate. The semiconductor fin includes a well region, a first doped region, and a second doped region. The first doped region and the second doped region are respectively adjacent to and being separated by a first portion of the well region. The device also includes a first gate structure on the semiconductor fin between the first doped region and the second doped region, and a first conductive structure electrically connecting the gate structure and the first doped region to a same potential. The ESD protection device can also have a third doped region and a second gate structure coupled to the same potential. The device also has a second conductive structure for connecting to a point between an external signal and a circuit to be protected.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 6, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10797030
    Abstract: Disclosed is a semiconductor package including a semiconductor chip, a first outer capacitor on the semiconductor chip including a first electrode and a second electrode, a second outer capacitor on the semiconductor chip including a first electrode pattern and a second electrode pattern, and a conductive pattern on the semiconductor chip and electrically connected to the first electrode of the first outer capacitor and the first electrode pattern of the second outer capacitor. The second electrode of the first outer capacitor is insulated from the second electrode pattern of the second outer capacitor.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: October 6, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangnam Jeong, IlJoon Kim, SunWon Kang
  • Patent number: 10790411
    Abstract: Embodiments of the present application relate to the use of quantum dots mixed with spacer particles. An illumination device includes a first conductive layer, a second conductive layer, and an active layer disposed between the first conductive layer and the second conductive layer. The active layer includes a plurality of quantum dots that emit light when an electric field is generated between the first and second conductive layers. The quantum dots are interspersed with spacer particles that do not emit light when the electric field is generated between the first and second conductive layers.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: September 29, 2020
    Assignee: Nanosys, Inc.
    Inventors: Jesse Manders, Christian Ippen, Donald Zehnder, Jonathan Truskier, Charles Hotz
  • Patent number: 10784371
    Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 10784255
    Abstract: A diode is provided having a plate-shaped semiconductor element that includes a first side and a second side, the first side being connected by a first connecting layer to a first metallic contact and the second side being connected by a second connecting layer to a second metallic contact, the first side having a diode element in a middle area and having a further diode element in an edge area of the first side, which has crystal defects as a result of a separating process of the plate-shaped semiconductor element, the first connecting layer only establishing an electrical contact to the diode element and not to the further diode element and, on the first side, the further diode element having an exposed contact, which may be electrically contacted by the first connecting layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 22, 2020
    Assignee: Robert Bosch GmbH
    Inventor: Alfred Goerlach
  • Patent number: 10784431
    Abstract: A device includes a first substrate formed of a first material that exhibits a threshold level of thermal conductivity. The threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates. In an embodiment, the device also includes a second substrate disposed in a recess of the first substrate, the second substrate formed of a second material that exhibits a second threshold level of thermal conductivity. The second threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates. In an embodiment, at least one qubit is disposed on the second substrate. In an embodiment, the device also includes a transmission line configured to carry a microwave signal between the first substrate and the second substrate.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 22, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Patryk Gumann, Salvatore Bernardo Olivadese, Jerry M. Chow
  • Patent number: 10777741
    Abstract: A method of forming a memory device that includes depositing a first dielectric material within a trench of composed of a second dielectric material; positioning a nanotube within the trench using chemical recognition to the first dielectric material; depositing a dielectric for cation transportation within the trench on the nanotube; and forming a second electrode on the dielectric for cation transportation, wherein the second electrode is composed of a metal.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Jianshi Tang, Ning Li
  • Patent number: 10777661
    Abstract: A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly silicon oxide (IPO) layer. The IPO layer can be formed by either depositing a silicon oxide layer or thermally growing a poly silicon oxide layer with minimal thickness variation. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 15, 2020
    Assignee: IPOWER SEMICONDUCTOR
    Inventor: Hamza Yilmaz
  • Patent number: 10777678
    Abstract: A semiconductor device includes: an active area including a drift layer of a first conductivity type; and a voltage blocking area arranged around the active area and including an field relaxation region having a second conductivity type, being provided in an upper portion of the drift layer, wherein a depth of the field relaxation region decreases toward outside, and a spatial-modulation portion is provided at an outer end of the field relaxation region.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 15, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Keiji Okumura
  • Patent number: 10777690
    Abstract: A capacitor structure includes a semiconductor substrate, a first vertical diffusion plate disposed in the semiconductor substrate, a first shallow trench isolation (STI) structure disposed in the semiconductor substrate and surrounding the first vertical diffusion plate, and a second vertical diffusion plate disposed in the semiconductor substrate and surrounding the first STI structure. The first vertical diffusion plate further includes a first lower portion that is part of the semiconductor substrate. The first lower portion is surrounded and electrically isolated by a first wafer-backside trench isolation structure. The first wafer-backside trench isolation structure is in direct contact with a bottom of the first STI structure.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: September 15, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Liang Chen
  • Patent number: 10770620
    Abstract: A light emitting diode includes a n-doped region, a p-doped region, and a light emitting region located between the n-doped region and a p-doped region. The n-doped region includes a first GaN layer, at least one n-doped second GaN layer located over the first GaN layer, an AlGaN dislocation blocking layer located over the at least one n-doped second GaN layer, and a n-doped third GaN layer located over the AlGaN dislocation blocking film.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: September 8, 2020
    Assignee: GLO AB
    Inventors: Zhen Chen, Fariba Danesh, Fan Ren, Shuke Yan
  • Patent number: 10763114
    Abstract: A method of fabricating a semiconductor device includes forming a semiconductor fin comprising a channel region for a fin field effect transistor (finFET). A gate oxide layer is then formed on the channel. The gate oxide layer is treated with a nitrogen containing agent so as to form a nitrogenous layer and an interfacial layer. The nitrogenous layer is then removed. A high-k dielectric layer is formed on the interfacial layer. A metal gate is formed on the high-k dielectric layer. The nitrogenous layer is removed by rinsing the semiconductor fin with deionized water. The gate oxide and interfacial layer contains the same material.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: September 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Andrew Joseph Kelly, Yusuke Oniki, Yasutoshi Okuno, Ta-Chun Ma
  • Patent number: 10748883
    Abstract: An encapsulation cover for an electronic package includes a cover body having a frontal wall provided with at least one optical element allowing light to pass through. The optical element is inserted into the encapsulation cover by overmolding into a through-passage of the frontal wall. A front face of the optical element is set back with respect to a front face of the frontal wall. The process for fabricating the encapsulation cover includes forming a stack of a sacrificial spacer on top of an optical element, with the stack placed into a cavity of a mold.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: August 18, 2020
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Jean-Michel Riviere
  • Patent number: 10741751
    Abstract: A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Nicholas A. Lanzillo, Benjamin D. Briggs, Chih-Chao Yang, Hsueh-Chung Chen, Lawrence A. Clevenger
  • Patent number: 10741603
    Abstract: A method for manufacturing an image sensor comprises: forming a trench around a photodiode, wherein the photodiode comprises a first doped region with a first conductivity type dopant formed in a semiconductor substrate with a second conductivity type dopant; forming a covering portion in the trench, the covering portion with the second conductivity type dopant covering at least a portion of a sidewall or a bottom wall of the trench, wherein a doping concentration of the covering portion is higher than a doping concentration of the semiconductor substrate; and diffusing the second conductivity type dopant in the covering portion into the semiconductor substrate so as to form a second doped region with the second conductivity type dopant surrounding the at least a portion of the sidewall or the bottom wall of the trench.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: August 11, 2020
    Assignee: HUAIAN IMAGING DEVICE MANUFACTURER CORPORATION
    Inventors: Xiaolu Huang, Xiangnan Lv, Yosuke Kitamura
  • Patent number: 10727368
    Abstract: Optoelectronic device modules having a silicon photonics transmitter die connected to a silicon interposer are described. In an example, the optoelectronic device module includes a silicon photonics transmitter die connected to a silicon interposer, and the silicon interposer is disposed between the silicon photonics transmitter die and a substrate. The silicon interposer provides an electrical interconnect between the silicon photonics transmitter die and the substrate, and reduces a likelihood that a hybrid silicon laser on the silicon photonics transmitter die will be damaged during module operation.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: Myung Jin Yim, Seungjae Lee, Sandeep Razdan