Abstract: A method of manufacturing a semiconductor device, including preparing a semiconductor wafer having first and second main surfaces opposite to each other, forming a photoresist film on the first main surface of the semiconductor wafer, forming a plurality of openings at predetermined positions in the photoresist film, cleaning the semiconductor wafer with water after the openings are formed, drying the semiconductor wafer by rotating the semiconductor wafer around a center axis that is orthogonal to the first main surface of the semiconductor wafer, to thereby generate a centrifugal force to cause the water that is left in the openings of the photoresist film to fly off the semiconductor wafer, and ion-implanting a predetermined impurity by a predetermined acceleration energy from the first main surface of the semiconductor wafer, using the photoresist film as a mask, after the drying. The drying process includes setting a rotational speed of the semiconductor wafer to be at most an upper limit value.

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

Abstract: Disclosed is a magnetic memory device including a first magnetic pattern that extends in a first direction and has a magnetization direction fixed in one direction, and a plurality of second magnetic patterns that extend across the first magnetic pattern. The second magnetic patterns extend in a second direction intersecting the first direction and are spaced apart from each other in the first direction. Each of the second magnetic patterns includes a plurality of magnetic domains that are spaced apart from each other in the second direction.

Abstract: A layer of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof has an upper surface and a bottom surface. The upper surface of a crystal layer of the group 13 nitride includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part, observed by cathode luminescence. The high-luminance light-emitting part includes a portion extending along an m-plane of the crystal of the group 13 nitride. The crystal of the nitride of the group 13 element contains oxygen atoms in a content of 1×1018 atom/cm3 or less, silicon atoms, manganese atoms, carbon atoms, magnesium atoms and calcium atoms in contents of 1×1017 atom/cm3 or less, chromium atoms in a content of 1×1016 atom/cm3 or less and chlorine atoms in a content of 1×1015 atom/cm3 or less.

Abstract: A piezo-junction device may be provided. The piezo-junction device comprises a piezoelectric element comprising two electrodes and piezoelectric material in-between, and a semiconductor junction device adjacent to the piezoelectric element such that one of the two electrodes of the piezoelectric element is in contact with the semiconductor junction device connecting the semiconductor junction device and the piezoelectric element electrically in series. Thereby, the semiconductor junction device and the piezoelectric element are together positioned in a fixed mechanical clamp such that the piezoelectric element with an applied electrical field applies strain to the semiconductor junction device causing a change in Fermi levels of the semiconductor junction device.

Abstract: A sensor can comprise a sensor die with a first sensor surface and a second sensor surface opposite to the first sensor surface. The sensor can further comprise a die pad component with a first pad surface and a second pad surface opposite to the first pad surface, wherein the sensor die is vertically stacked with the die pad component, with the second sensor surface oriented toward the first pad surface. The sensor can further comprise a lead frame component with a first frame surface and a second frame surface opposite to the first frame surface, the die pad component is vertically stacked with the lead frame component, wherein the second pad surface is oriented toward the first frame surface, the second pad surface is isolated from the second frame surface, and the lead frame component is electrically connected to the sensor die.

Abstract: The disclosure provides an electronic device and a method of manufacturing an electronic device. The electronic device includes a first substrate, a plurality of light-emitting dies, a transparent material layer, a sealing material, and a second substrate. The plurality of light-emitting dies are disposed on the first substrate. The transparent material layer is disposed on the first substrate. The sealing material is disposed on the first substrate and surrounds the transparent material layer. The second substrate is adhered to the first substrate through the transparent material layer and the sealing material.

Abstract: An integrated circuit includes gate-all-around (GAA) nanowire transistors, GAA nanosheet transistors, and planar devices on the same substrate. Gate dielectric layers of the GAA nanowire transistors and the GAA nanosheet transistors have substantially the same thickness which is smaller than the thickness of the gate dielectric layer of the planar devices. The channel width of the planar devices is greater than the channel width of the GAA nanosheet transistors, which is greater than the channel width of the GAA nanowire transistors.

Abstract: First p+-type regions are provided directly beneath trenches, separate from a p-type base region and facing bottoms of the trenches in a depth direction. The first p+-type regions are exposed at the bottoms of the trenches and are in contact with a gate insulating film at the bottoms of the trenches. Second p+-type regions are each provided between (mesa region) adjacent trenches, separate from the first p+-type regions and the trenches. Drain-side edges of the second p+-type regions are positioned closer to a source side than are drain-side edges of the first p+-type regions. In each mesa region, an n+-type region is provided separate from the first p+-type regions and the trenches. The n+-type regions are adjacent to and face the second p+-type regions in the depth direction.

Abstract: An implementation of a MEMS device includes a constrained diaphragm comprising a surface, the diaphragm having a net compressive stress; and a backplate comprising a surface facing the surface of the diaphragm, the surface of the backplate having a center, and a post extending from the surface of the backplate, wherein the post is located at or near a center of the surface and limits a maximum deflection of the diaphragm.

Abstract: A MEMS device can include a first support layer, a second support layer, and a solid dielectric suspended between the first support layer and the second support layer. The solid dielectric can move relative to the first support layer and the second support layer and can include a plurality of apertures. The MEMS device can include a first plurality of electrodes coupled to the first support layer and the second support layer and extending through a first subset of the plurality of apertures. The MEMS device can include a second plurality of electrodes coupled to the first support layer and extending partially into a second subset of the plurality of apertures. The MEMS device can include a third plurality of electrodes coupled to the second support layer and extending partially into a third subset of the plurality of apertures.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a substrate, a first electrode structure on the substrate, the first electrode structure including first insulating patterns and first electrode patterns, the first insulating patterns alternately stacked with the first electrode patterns, a second electrode pattern on a sidewall of the first electrode structure, and a data storage film on a sidewall of the second electrode pattern. The data storage film has a variable resistance.

Abstract: A chip-scale package type light emitting diode includes a first conductivity type semiconductor layer, a mesa, a second conductivity type semiconductor layer, a transparent conductive oxide layer, a dielectric layer, a lower insulation layer, a first pad metal layer, and a second pad metal layer, an upper insulation layer. The upper insulation layer covers the first pad metal layer and the second pad metal layer, and includes a first opening exposing the first pad metal layer and a second opening exposing the second pad metal layer. The openings of the dielectric layer include openings that have different sizes from one another.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.

Abstract: A layer of a crystal of a group 13 nitride selected from gallium nitride, aluminum nitride, indium nitride and the mixed crystals thereof has an upper surface and a bottom surface. The upper surface includes a linear high-luminance light-emitting part and a low-luminance light-emitting region adjacent to the high-luminance light-emitting part. The high-luminance light-emitting part includes a portion extending along an m-plane of the crystal of the group 13 nitride. A normal line to the upper surface has an off-angle of 2.0° or less with respect to <0001> direction of the crystal of the nitride of the group 13 element.

Abstract: A first electrode of a MEMS device can be oriented lengthwise along and parallel to an axis, and can have a first end and a second end. A second electrode can be oriented lengthwise along and parallel to the axis and can have a first end and a second end. A third electrode can be oriented lengthwise along and parallel to the axis and can have a first end and a second end. The first, second, and third electrodes can each be located at least partially within an aperture of a plurality of apertures of a solid dielectric that can surround the second electrode second end and the third electrode first end. The second electrode first end and the third electrode second end can be located outside of the solid dielectric.

Abstract: A method for manufacturing a semiconductor device includes implanting gas ions in a donor wafer and bonding the donor wafer to a carrier wafer to form a compound wafer. The method also includes subjecting the compound wafer to a thermal treatment to cause separation along a delamination layer and growing an epitaxial layer on a portion of separated compound wafer to form a semiconductor device layer. The method further includes cutting the carrier wafer.

Abstract: A light emitting device for a display including a first LED sub-unit, a second LED sub-unit disposed on the first LED sub-unit, a third LED sub-unit disposed on the second LED sub-unit, electrode pads disposed under the first LED sub-unit, each of the electrode pads being electrically connected to at least one of the first, second, and third LED sub-units, and lead electrodes electrically connected to the electrode pads and extending outwardly from the first LED sub-unit.

Abstract: There is provided an aluminum nitride laminate member including: a sapphire substrate having a base surface on which bumps are distributed periodically, each bump having a height of smaller than or equal to 500 nm; and an aluminum nitride layer grown on the base surface and having a flat surface, there being substantially no voids in the aluminum nitride layer.

Abstract: A light emitting device for a display includes first LED sub-unit, second LED, and third LED sub-units, an insulating layer substantially covering the first, second, and third LED sub-units, and electrode pads electrically connected to the first, second, and third LED sub-units, in which the first LED sub-unit is disposed on a partial region of the second LED sub-unit, the second LED sub-unit is disposed on a partial region of the third LED sub-unit, the insulating layer has openings for electrical connection between the electrode pads, a common electrode pad is connected to the first, second, and third LED sub-units through the openings in the insulating layer, first, second, and third electrode pads are connected to the first, second, and third LED sub-units, respectively, through at least one of the openings, and the first, second, and third LED sub-units are configured to be independently driven using the electrode pads.