Abstract: A package substrate and a semiconductor structure with the package substrate are provided. The package substrate includes a body and a conductive layer. The body includes an opening region. The conductive layer is disposed at the opening region. The conductive layer includes a first conductive bridge and a second conductive bridge. The first conductive bridge and the second conductive bridge are disposed at intervals. The first conductive bridge is provided with at least one first via. The first conductive bridge and the second conductive bridge are disposed at intervals in the opening region.

Abstract: Aspects of the present disclosure provide a method for fabricating a semiconductor structure. For example, the method can include forming a stack of metal structures on a substrate, the stack of metal structures including multiple metal structures that are vertically stacked over and electrically separated from one another, each of the metal structures including a ring and one or more pad contacts extending from the ring, the rings of the metal structures being vertically aligned with one another. The method can also include forming one or more channel structures within the rings of the metal structures, the channel structures being electrically separated from one another and electrically separated from the substrate. The method can also include forming one or more interconnections that extend from a position above the stack of metal structures to corresponding one or more of the pad contacts of the metal structures.

Abstract: A novel material is provided. A composite oxide semiconductor in which a first region and a plurality of second regions are mixed is provided. Note that the first region contains at least indium, an element M (the element M is one or more of Al, Ga, Y, and Sn), and zinc, and the plurality of second regions contain indium and zinc. Since the plurality of second regions have a higher concentration of indium than the first region, the plurality of second regions have a higher conductivity than the first region. An end portion of one of the plurality of second regions overlaps with an end portion of another one of the plurality of second regions. The plurality of second regions are three-dimensionally surrounded with the first region.

Abstract: A support substrate supports an electronic chip. An encapsulation coating on the support substrate coats the electronic chip. The encapsulation coating includes a trench surrounding the electronic chip. A heat sink is mounted to the encapsulation coating above the electronic chip. The heat sink is fixed to the encapsulation coating by an adhesive material and a thermal interface material layer is present between the electronic chip and the heat sink. The trench is positioned between the thermal interface material layer and the adhesive material.

Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.

Abstract: A semiconductor device has a substrate and a semiconductor die disposed over the substrate. A tape is disposed over the semiconductor die. An encapsulant is deposited over the substrate, semiconductor die, and tape. The tape is removed to leave a cavity in the encapsulant over the semiconductor die. A shielding layer is formed over the encapsulant and semiconductor die. A heat spreader is disposed over the shielding layer. The heat spreader includes a protrusion extending into the cavity of the encapsulant.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes an interconnect structure disposed over a semiconductor substrate. A dielectric structure is disposed over the interconnect structure. A plurality of cavities are disposed in the dielectric structure. A microelectromechanical system (MEMS) substrate is disposed over the dielectric structure, where the MEMS substrate comprises a plurality of movable membranes, and where the movable membranes overlie the cavities, respectively. A plurality of fluid communication channels are disposed in the dielectric structure, where each of the fluid communication channels extend laterally between two neighboring cavities of the cavities, such that each of the cavities are in fluid communication with one another.

Abstract: A magnetic apparatus includes a first structure including a first non-magnetic material, a second structure including a second non-magnetic material on a first portion of the first structure, a third structure including the second non-magnetic material on a second portion of the first structure. The magnetic apparatus further includes a first magnetic structure adjacent to a first sidewall of the second structure, a second magnetic structure adjacent to a first sidewall of the third structure, a third magnetic structure adjacent to a second sidewall of the second structure, adjacent to a second sidewall of the third structure and extends onto a third portion of the first structure. A magnet is coupled with the first, second and third magnetic structures.

Abstract: A flexible display device including a substrate, a light emitting layer, a first insulating layer, and a conductive layer. The substrate includes a bent region and a non-bent region. The light emitting layer overlaps the non-bent region. The first insulating layer is disposed on the substrate. The conductive layer is disposed on the first insulating layer. A sidewall of the first insulating layer includes a first tapered surface. The first tapered surface includes at least three curved surface portions continuously arranged with one another.

Abstract: Processes and structures resulting therefrom for the improvement of high speed signaling integrity in electronic substrates of integrated circuit packages, which is achieved with the formation of airgap structures within dielectric material(s) between adjacent conductive routes that transmit/receive electrical signals, wherein the airgap structures decrease the capacitance and/or decrease the insertion losses in the dielectric material used to form the electronic substrates.

Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer. A top surface of the first conductive plug is greater than a bottom surface of the first conductive plug. The semiconductor device structure further includes a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug.

Abstract: A semiconductor device structure includes a first dielectric layer disposed over a semiconductor substrate, and a second dielectric layer disposed over the first dielectric layer. The semiconductor device structure also includes a first conductive plug disposed in the first dielectric layer. A top surface of the first conductive plug is greater than a bottom surface of the first conductive plug. The semiconductor device structure further includes a second conductive plug disposed in the second dielectric layer and directly over the first conductive plug.

Abstract: A semiconductor device has an active region through which a main current flows, a gate ring region surrounding a periphery of the active region, a source ring region surrounding a periphery of the gate ring region, and a termination region surrounding a periphery of the source ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and further, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film, a first first-electrode, a first plating film, and a second electrode. The semiconductor device has, in the source ring region, a second first-electrode provided at a surface of the second semiconductor layer, and a second plating film provided on the second first-electrode.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first device and a second device disposed adjacent to the first device; a conductive pillar disposed adjacent to the first device or the second device; a molding surrounding the first device, the second device and the conductive pillar; and a redistribution layer (RDL) over the first device, the second device, the molding and the conductive pillar, wherein the RDL electrically connects the first device to the second device and includes an opening penetrating the RDL and exposing a sensing area over the first device.

Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.

Abstract: Provided is a semiconductor power device. The device includes: at least one p-type body region located on the top of an n-type drift region, a first n-type source region and a second n-type source region located within the p-type body region, a first gate structure configured to control a first current channel between the first n-type source region and the n-type drift region to be turned on or off; and a second gate structure configured to control a second current channel between the second n-type source region and the n-type drift region to be turned on or off. The second gate structure is recessed in the n-type drift region.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a conductive region, an end region positioned at a portion where the conductive region ends, and a connection region positioned between the conductive region and the end region. The conductive region includes: an n+ type substrate; an n? type layer positioned at the first surface of the n+ type substrate; and a p type region positioned on the n? type layer, and a gate electrode that fills an inside of a trench penetrating the p type region and positioned in the n? type layer, and a side wall of the trench positioned at the portion where the conductive region ends is inclined.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate a substrate, a first electrode structure on the substrate, the first electrode structure including first insulating patterns and first electrode patterns, the first insulating patterns alternately stacked with the first electrode patterns, a second electrode pattern on a sidewall of the first electrode structure, and a data storage film on a sidewall of the second electrode pattern. The data storage film has a variable resistance.

Abstract: Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a source structure, a stacked conductive layer that overlaps with the source structure, a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer, a stacked insulating layer disposed between the first and second select conductive layers and the stacked conductive layer, and a separation insulating structure provided between the first select conductive layer and the second select conductive layer.

Abstract: The present disclosure provides a semiconductor structure and a forming method thereof. The semiconductor structure includes: a substrate and an epitaxial layer disposed on the substrate. At least a part of the epitaxial layer is doped with metal atoms, and the doping concentration of the metal atoms at the bottom surface of the epitaxial layer near the substrate is larger than 1×1017 atoms/cm3.