Patents Examined by Sanjiv Shah
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Patent number: 11086522Abstract: Automated port selection for data migration includes an algorithm that selects a set of SAN ports with the following properties: the selected ports have the least port utilization among all possible port selections; the number of independent data paths between the selected ports is no smaller than a user configurable minimum number; and the difference between the aggregate bandwidth of the ports on both arrays is minimized.Type: GrantFiled: September 23, 2016Date of Patent: August 10, 2021Assignee: EMC IP HOLDING COMPANY LLCInventors: Xuedong Jiang, John Copley, Michael Specht
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Patent number: 11023318Abstract: A system and method is provided for fast random access erasure encoded storage. An exemplary method includes writing data to an append-only data log that includes data log extents that are each associated with data that is mapped to corresponding offset range of a virtual file of a client and storing the append-only data log as a sequence of data chunks each allocated on one or more one storage disks. Moreover, the method determines an amount of useful data in one or more data chunks and, when the amount of useful data in the data chunk is less than a predetermined threshold, appending the useful data from the data chunk to an end of the append-only data log. Finally, the data log is cleaned by releasing the one or more data chunk from the append-only data log after the useful data is appended to the append-only data log.Type: GrantFiled: June 21, 2018Date of Patent: June 1, 2021Assignee: Virtuozzo International GmbHInventors: Oleg Volkov, Andrey Zaitsev, Alexey Kuznetzov, Pavel Emelyanov, Alexey Kobets, Kirill Korotaev
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Patent number: 11016676Abstract: Systems, methods, and computer program products for distributed data storage. A spot defragmentation method commences upon receiving an incoming storage I/O command to access a subject logical object that is composed of subject logical data blocks. The method continues by retrieving a block map that characterizes spatial relationships between the subject logical data blocks and instances of respective subject physical data blocks that store the subject logical object on a storage device. During processing of the incoming storage I/O command, the method determines occurrences of, and locations of one or more fragmented physical data blocks. A defragmentation operation is initiated to coalesce the fragmented physical data blocks to another location. The defragmentation operation is initiated before completing the storage I/O command.Type: GrantFiled: February 9, 2016Date of Patent: May 25, 2021Assignee: Nutanix, Inc.Inventors: Manosiz Bhattacharyya, Bharat Kumar Beedu, Parthasarathy Ramachandran
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Patent number: 10996898Abstract: A storage system in one embodiment comprises a plurality of storage devices and an associated storage controller. The storage controller is configured to identify a dataset to be scanned to generate a capacity release estimate for prospective deletion of that dataset, to designate a content-based signature prefix to be utilized in the scan, and to scan logical address mapping information for the dataset to identify one or more pages of the dataset that have the designated content-based signature prefix. The scanning further comprises, for each such identified page, determining a reference count of the page, and responsive to the reference count of the page having a particular value, determining a compressibility measure for the page. The storage controller generates the capacity release estimate for prospective deletion of the dataset based at least in part on the one or more page compressibility measures determined as part of the scan.Type: GrantFiled: May 29, 2018Date of Patent: May 4, 2021Assignee: EMC IP Holding Company LLCInventors: David Meiri, Anton Kucherov
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Patent number: 10866757Abstract: A production host for hosting a multi-instanced application includes a persistent storage and a resource manager. The persistent storage stores a resource registration associated with a plurality of instances of the multi-instanced application and a resource backup registration associated with backups, of the multi-instance application, that are stored in backup storage.Type: GrantFiled: September 26, 2018Date of Patent: December 15, 2020Assignee: EMC IP Holding Company LLCInventors: Jigar Premajibhai Bhanushali, Sunil Yadav, Aneesh Kumar Gurindapalli, Sunder Ramesh Andra, Amarendra Behera, Shelesh Chopra
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Patent number: 10740005Abstract: Described are techniques for processing requests at a data storage system. A request is received from a client to perform an operation with respect to a first data portion stored on physical storage devices of the data storage system. The first data portion is exposed through a set of at least two data nodes each accessing a same copy of the first data portion stored on the physical storage devices. The request is received at a first of the data nodes of the set. The request is processed with respect to the first data portion using the same copy accessible to each of data nodes of the set. The physical storage devices may be configured in a RAID group and the data nodes, optionally along with a name node providing metadata, may be embedded in the data storage system and execute in a virtualized environment.Type: GrantFiled: September 29, 2015Date of Patent: August 11, 2020Assignee: EMC IP Holding Company LLCInventors: Stephen Richard Ives, Hongliang Tang, Kevin Rodgers, Sethu N. Madhavan
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Patent number: 10713190Abstract: Disclosed approaches for managing a translation look-aside buffer (TLB) have a bus master circuit that issues a read request that specifies a first virtual address of a first page. In response to a sequential access being identified and before data of the first page is returned, the bus master circuit issues a dummy read request that specifies a second virtual address of a second page. A TLB has mappings of virtual addresses to physical addresses, and a translation logic circuit translates virtual addresses to physical addresses. The translation logic circuit signals a miss in response to absence of a virtual address in the TLB. A control circuit in the MMU determines from a page table a mapping of a virtual address to a physical address in response to the signaled miss. The translation logic circuit updates the TLB circuit with the mapping.Type: GrantFiled: October 11, 2017Date of Patent: July 14, 2020Assignee: Xilinx, Inc.Inventor: Ygal Arbel
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Patent number: 10262721Abstract: The present disclosure includes apparatuses and methods for cache invalidate. An example apparatus comprises a bit vector capable memory device and a channel controller coupled to the memory device. The channel controller is configured to cause a bulk invalidate command to be sent to a cache memory system responsive to receipt of a bit vector operation request.Type: GrantFiled: March 10, 2016Date of Patent: April 16, 2019Assignee: Micron Technology, Inc.Inventor: Richard C. Murphy
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Patent number: 9946719Abstract: An apparatus includes a processor component of a first node device caused to receive data block encryption data and an indication of size of an encrypted data block distributed to the first node device for decryption, and in response to the data set being of encrypted data: receive an indication of the quantity of sub-blocks within the encrypted data block, and a hashed identifier for each data sub-block; use the data block encryption data to decrypt the encrypted data block to regenerate data set portions from the data sub-blocks; analyze the hashed identifier of each data sub-block to determine whether all data set portions are distributed to the first node device for processing; and in response to a determination that at least one data set portion is to be distributed to a second node device for processing, transmit the at least one data set portion to the second node device.Type: GrantFiled: September 1, 2017Date of Patent: April 17, 2018Assignee: SAS Institute Inc.Inventors: Brian Payton Bowman, Mark Kuebler Gass, III
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Patent number: 9946718Abstract: An apparatus may include a processor component caused to: generate map entries in map data descriptive of encrypted data blocks within a data file; use first map block encryption data to encrypt a first map extension of the map data; transmit the encrypted first map extension for storage within the data file; store the first map block encryption data within the second map extension; use second map block encryption data to encrypt a second map extension of the map data after storage of the first map block encryption data therein; transmit encrypted second map extension for storage within the data file; store the second map block encryption data within the map base; use third map block encryption data to encrypt a map base of the map data after storage of the second map block encryption data therein; and transmit the encrypted map base for storage within the data file.Type: GrantFiled: September 1, 2017Date of Patent: April 17, 2018Assignee: SAS Institute Inc.Inventors: Brian Payton Bowman, Mark Kuebler Gass, III
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Patent number: 9898361Abstract: Methods and apparatus are provided for multi-tier detection and decoding in flash memory devices. Data from a flash memory device is processed by obtaining one or more read values for at least one bit in a given page of the flash memory device; converting the one or more read values for the at least one bit to a reliability value; performing an initial decoding of the at least one bit in a given page using the reliability value; and performing an additional decoding of the at least one bit in the given page if the initial decoding is not successful, wherein the additional decoding uses one or more of additional information for the given page and at least one value for at least one bit from at least one additional page.Type: GrantFiled: December 31, 2012Date of Patent: February 20, 2018Assignee: Seagate Technology LLCInventors: Erich F. Haratsch, Abdel Hakim S. Alhussien
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Patent number: 9880543Abstract: A method for transmitting and receiving data between a micro processing unit (MPU) and a memory operating with different operating voltages in a programmable logic controller (PLC) is provided. In one embodiment, the method includes outputting, by the MPU, a chip select (CS) signal and an address signal to read requested data from the memory, outputting, by an OR gate, an activation signal for activating a data input buffer, the OR gate receiving the CS signal and the address signal, and outputting, by an access signal output buffer, a memory access signal for operation of the memory, the access signal output buffer receiving the CS signal and the address signal. The method further includes outputting the requested data to the data input buffer, and outputting, by the data input buffer, the requested data to the MPU when the requested data is received by the data input buffer from the memory.Type: GrantFiled: September 25, 2015Date of Patent: January 30, 2018Assignee: LSIS CO., LTD.Inventor: Jo Dong Park
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Patent number: 9870400Abstract: Analyzing a managed runtime cache is provided. A heap associated with a managed runtime environment, where the heap includes an N-generation cache or a plurality of objects associated with a program operating within a managed runtime environment is identified. A snapshot of the heap is produced, wherein the snapshot identifies a memory location for each object of the plurality of objects at which the object is stored. A generation of each of the plurality of objects based, at least in part, on the memory location of the object is determined. One or more suggestions based, at least in part, on the memory location of the plurality of objects is provided.Type: GrantFiled: August 4, 2015Date of Patent: January 16, 2018Assignee: International Business Machines CorporationInventors: Richard N. Chamberlain, Howard J. Hellyer, Matthew F. Peters, Adam J. Pilkington
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Patent number: 9830094Abstract: A system, method, and computer program product is described for providing dynamic enabling and/or disabling of protection information (PI) in array systems during operation. A storage system receives a request to transition a volume from PI disabled to PI enabled during regular operation. The storage system synchronizes and purges the cache associated with the target volume. The storage system initiates an immediate availability format (IAF-PI) process to initialize PI for the associated data blocks of the volume's storage devices. The storage system continues receiving I/O requests as the IAF-PI process sweeps through the storage devices. The storage system inserts and checks PI for the write data as it is written to the storage devices. The storage system inserts PI for requested data above the IAF-PI boundary and checks PI for requested data below the IAF-PI boundary. The transition remains an online process that avoids downtime.Type: GrantFiled: June 23, 2015Date of Patent: November 28, 2017Assignee: NetApp, Inc.Inventors: Mahmoud K. Jibbe, Charles D. Binford, Wei Sun
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Patent number: 9753813Abstract: Persistent storage for a master copy is provided using operation numbers. A master copy can include a persistent key-value store such as a B-tree with references to corresponding data. When provisioning a slave copy, the master copy sends a point-in-time copy of the B-tree to the slave copy, which stores a copy of the B-tree, allocates the necessary space, and updates the references of the B-tree to point to a local storage before the data is transferred. When writing the data to persistent storage, a snapshot created on the master copy is an operation that is replicated to the slave copy. The snapshot is generated using a volume view that includes changes to chunks of data of the master copy since a previous snapshot, as determined using the operation number for the previous snapshot. Data (and metadata) for the snapshot is written to persistent storage while new EO operations are processed.Type: GrantFiled: September 25, 2015Date of Patent: September 5, 2017Assignee: Amazon Technologies, Inc.Inventors: Jianhua Fan, Benjamin Arthur Hawks, Norbert Paul Kusters, Nachiappan Arumugam, Danny Wei, John Luther Guthrie, II
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Patent number: 9746986Abstract: A storage system includes a plurality of storage devices, including a first storage device and an information processor apparatus for managing the storage system. The first storage device is configured to select a second storage device coupled over a network with the information processor apparatus from among the plurality of storage devices, and assign a representative address such as an Internet Protocol (IP) address to be used for communication with the information processor apparatus to the selected second storage device. The second storage device is configured to receive a request addressed to the representative address from the information processor apparatus, and transfer the request to a third storage device among the plurality of storage devices to process the request. An assigned representative address may be canceled when a storage device fails and an internal IP address may be assigned. Storage devices may be selected based on load and the need for cable or hardwired connections may be reduced.Type: GrantFiled: December 18, 2015Date of Patent: August 29, 2017Assignee: FUJITSU LIMITEDInventors: Takashi Kuwayama, Tsuyoshi Uchida
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Patent number: 9632929Abstract: A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.Type: GrantFiled: February 8, 2007Date of Patent: April 25, 2017Assignee: Google Inc.Inventors: Suresh Natarajan Rajan, Keith R. Schakel, Michael John Sebastian Smith, David T. Wang, Frederick Daniel Weber
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Patent number: 9563359Abstract: A system is provided for transforming an in-use RAID array from a first array configuration having a first parameter to a second array configuration having a second parameter while preserving a logical data structure of the RAID array. The system includes an extent reservation component, and a data migration component for reading unmigrated data from an area of an array arranged according to the first array configuration and writing the data to an area of the array arranged according to the second array configuration using reserved extents to store migrated data. The system also includes a first I/O component for performing I/O according to the first array configuration on unmigrated data prior to its reading by the data migration component, and a second I/O component for performing I/O according to the second array configuration on the migrated data after writing the migrated data.Type: GrantFiled: October 19, 2015Date of Patent: February 7, 2017Assignee: International Business Machines CorporationInventors: Joanna K. Brown, Matthew J. Fairhurst, William J. Scales, Mark B. Thomas
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Patent number: 9558085Abstract: An administrator provisions a virtual disk in a remote storage platform and defines policies for that virtual disk. A virtual machine writes to and reads from the storage platform using any storage protocol. Virtual disk data within a failed storage pool is migrated to different storage pools while still respecting the policies of each virtual disk. Snapshot and revert commands are given for a virtual disk at a particular point in time and overhead is minimal. A virtual disk is cloned utilizing snapshot information and no data need be copied. Any number of Zookeeper clusters are executing in a coordinated fashion within the storage platform, thus increasing overall throughput. A timestamp is generated that guarantees a monotonically increasing counter, even upon a crash of a virtual machine. Any virtual disk has a “hybrid cloud aware” policy in which one replica of the virtual disk is stored in a public cloud.Type: GrantFiled: July 2, 2014Date of Patent: January 31, 2017Assignee: Hedvig, Inc.Inventor: Avinash Lakshman
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Patent number: 9552170Abstract: The memory area managing unit 22 (a) sets a protect flag to each virtual area allocated in a virtual memory space, the protect flag indicating whether a use of the virtual area has been finished or not, and (b) when a part or all of a first virtual area would overlap another second virtual area due to expansion or movement of the first virtual area, allows the expansion or the movement of the first virtual area accompanying with overlapping the second virtual area, if the protect flag of the second virtual area indicates that a use of the second virtual area has been finished. If the expansion or the movement is allowed, the memory pool managing unit 23 adds a physical area in a physical memory space corresponding to an overlapping part of the first and second virtual areas into a memory pool to map to another virtual area.Type: GrantFiled: January 23, 2013Date of Patent: January 24, 2017Assignee: Kyocera Document Solutions, Inc.Inventors: Masato Tanba, Takashi Toyoda