Patents Examined by Sara Crane
  • Patent number: 7262427
    Abstract: A phase change device includes a first contact electrode structure a phase change material and a first insulating material between the phase change material and the first contact electrode structure and a second contact electrode in contact with the phase change material. A contact structure formed in the first insulating material between the first contact electrode structure and the phase change material is also included. The contact structure is formed by an insulating material breakdown process. A method of forming a phase change device is also described.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: August 28, 2007
    Assignee: Macronix International Co., Ltd.
    Inventors: Ming Hsiu Lee, Yi Chou Chen
  • Patent number: 7262093
    Abstract: A flash memory cell is provided. The flash memory cell includes a substrate having a source and a drain formed therein, a bit line contact formed above the drain, a control gate formed above the substrate, a spacer floating gate formed above the substrate and adjacent to the control gate, and a first spacer formed between the bit line contact and the control gate, wherein the first spacer is in contact with both the bit line contact and the control gate.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: August 28, 2007
    Assignee: ProMOS Technologies, Inc.
    Inventor: Tings Wang
  • Patent number: 7259429
    Abstract: It is an object of the present invention to provide a semiconductor display device using a protective circuit in which dielectric breakdown is prevented more effectively. In the invention, in the cases that a first interlayer insulating film is formed covering a TFT used for a protective circuit and a second interlayer insulating film, which is an insulating coating film, is formed covering a wiring formed over the first interlayer insulating film, a wiring for connecting the TFT to other semiconductor elements is formed so as to be in contact with the surface of the second interlayer insulating film so as to secure a path discharging charge accumulated in the surface of the second interlayer insulating film. Note that the TFT used for the protective diode is a so-called diode-connected TFT in which either of the first terminal or the second terminal is connected to a gate electrode.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: August 21, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 7259396
    Abstract: The invention relates to a light source comprising a light-emitting element, which emits light in a first spectral region, and comprising a luminophore, which comes from the group of alkaline-earth orthosilicates and which absorbs a portion of the light emitted by the light source and emits light in another spectral region. According to the invention, the luminophore is an alkaline-earth orthosilicate, which is activated with bivalent europium and whose composition consists of: (2-x-y)SrOx(Ba, Ca)O (1-a-b-c-d)SiO2aP2O5bAl2O3cB2O3dGeO2: y Eu2+ and/or (2-x-y)BaOx((Sr, Ca)O (1-a-b-c-d)SiO2aP2O5bAl2O3cB2O3dGeO2: y Eu2+. The desired color (color temperature) can be easily adjusted by using a luminophore of the aforementioned type.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: August 21, 2007
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Stefan Tasch, Peter Pachler, Gundula Roth, Walter Tews, Wolfgang Kempfert, Detlef Starick
  • Patent number: 7259442
    Abstract: A selectively doped trench isolation device is provided. The trench isolation device of the preferred embodiment includes a semiconductor substrate having a trench. A thin field oxide layer is grown on the side walls of the trench, and the trench is filled with a heavily doped polysilicon. The work function difference between the substrate and the heavily doped polysilicon increases the field threshold voltage of the gated trench isolation device so that smaller isolation structures can be formed between adjacent active devices in higher density integrated circuits.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: August 21, 2007
    Assignee: Micron Technology, Inc.
    Inventors: David Y. Kao, Rongsheng Yang
  • Patent number: 7256083
    Abstract: A method of making a semiconductor structure includes depositing a nitride layer, on a metallic layer, by PECVD. The metallic layer is on a gate layer containing silicon, and the gate layer is on a semiconductor substrate.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: August 14, 2007
    Assignee: Cypress Semiconductor Corporation
    Inventors: Alain Blosse, Krishnaswamy Ramkumar
  • Patent number: 7256472
    Abstract: A bipolar transistor and method of making a bipolar transistor is disclosed. In one embodiment, the bipolar transistor includes a polysilicon layer into which impurity atoms are inserted, thereby reducing the layer resistance.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: August 14, 2007
    Assignee: Infineon Technologies AG
    Inventors: Josef Bock, Thomas Meister, Andriy Romanyuk, Herbert Schäfer
  • Patent number: 7256074
    Abstract: Methods for packaging microelectronic devices, microelectronic workpieces having packaged dies, and microelectronic devices are disclosed herein. One aspect of the invention is directed toward a microelectronic workpiece comprising a substrate having a device side and a backside. In one embodiment, the microelectronic workpiece further includes a plurality of dies formed on the device side of the substrate, a dielectric layer over the dies, and a plurality of bond-pads on the dielectric layer. The dies have integrated circuitry and a plurality of bond-pads electrically coupled to the integrated circuitry. The ball-pads are arranged in ball-pad arrays over corresponding dies on the substrate. The microelectronic workpiece of this embodiment further includes a protective layer over the backside of the substrate. The protective layer is formed on the backside of the substrate from a material that is in a flowable state and is then cured to a non-flowable state.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: August 14, 2007
    Assignee: Micron Technology, Inc.
    Inventor: James L. Voelz
  • Patent number: 7257830
    Abstract: A mobile electronic apparatus functions as an image medium reproducer, and, in particular, a moving image, such as a DVD reproducer. The mobile electronic apparatus has a mobile body, and a mobile stand detachably connectable with the mobile body. While the mobile apparatus body is connected to the mobile apparatus stand, the mobile apparatus body performs auralization and visualization of at least one A/V (Audio/Video) signal based on at least one input A/V signal from an A/V storage medium and at least one input body control signal output from the mobile apparatus stand, and outputs at least one stand control signal controlling the A/V signal output by the mobile apparatus stand. When the mobile apparatus body is disconnected from the mobile apparatus stand, the mobile apparatus body operates as an independent mobile electronic apparatus.
    Type: Grant
    Filed: February 13, 2004
    Date of Patent: August 14, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Il Cha, Joo-young Kwon
  • Patent number: 7256449
    Abstract: An electrically erasable and programmable read only memory (EEPROM) device may include: a gate oxide layer on a semiconductor substrate, the gate oxide layer including a first segment of a first thickness, a second segment of a second thickness, and a tunneling third segment of a third thickness, the second thickness being thicker than the first thickness and the third thickness being thinner than the first thickness; a floating junction region formed under a portion of the gate oxide layer in the semiconductor substrate; and a floating gate, an insulating layer pattern, and a control gate which are sequentially formed, respectively, on the gate oxide layer.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: August 14, 2007
    Assignee: Samsung Electronics, Co., Ltd.
    Inventors: Sung-Taeg Kang, Seong-Gyun Kim
  • Patent number: 7256486
    Abstract: The packaging device includes a substrate, a mounting pad, a connecting pad and an interconnecting element. The substrate is substantially planar and has opposed major surfaces. The mounting pad is conductive and is located on one of the major surfaces. The connecting pad is conductive and is located on the other of the major surfaces. The conductive interconnecting element extends through the substrate and electrically interconnects the mounting pad and the connecting pad. The packaging device has a volume that is only a few times that of the semiconductor die and can be fabricated from materials that can withstand high-temperature die attach processes. The packaging device can be configured as the only packaging device used in the semiconductor device or as a submount for a semiconductor die that requires a high-temperature die attach process.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: August 14, 2007
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Kong Weng Lee, Kee Yean Ng, Yew Cheong Kuan, Gin Ghee Tan, Cheng Why Tan
  • Patent number: 7256092
    Abstract: A high-voltage semiconductor MOS process that is fully compatible with low-voltage MOS process is provided. The high-voltage N/P well are implanted into the substrate prior to the definition of active areas. The channel stop doping regions are formed after the formation of field oxide layers, thus avoiding lateral diffusion of the channel stop doping regions. In addition, the grade drive-in process used to activate the grade doping regions in the high-voltage device area and the gate oxide growth of the high-voltage devices are performed simultaneously.
    Type: Grant
    Filed: July 25, 2004
    Date of Patent: August 14, 2007
    Assignee: United Microelectronics Corp.
    Inventors: Jung-Ching Chen, Jy-Hwang Lin, Sheng-Hsiung Yang, Jim Su
  • Patent number: 7256456
    Abstract: A semiconductor IC device includes a base substrate comprising P?-type silicon, a first P+-type silicon layer is provided on the base substrate, and an N+-type silicon layer and a second P+-type silicon layer are provided in the same layer thereon. The impurity concentration of the first P+-type silicon layer and the N+-type silicon layer is higher than that of the base substrate. Also, a buried oxide layer and an SOI layer are provided on the entire upper surface of the N+-type silicon layer and the second P+-type silicon layer. The first P+-type silicon layer is connected to ground potential wiring GND, and the N+-type silicon layer is connected to power-supply potential wiring VDD. Accordingly, a decoupling capacitor, which is connected in parallel to the power supply, is formed between the P+-type silicon layer and the N+-type silicon layer.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: August 14, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Hiroaki Ohkubo, Masayuki Furumiya, Ryota Yamamoto, Yasutaka Nakashiba
  • Patent number: 7256461
    Abstract: The present invention provides a combinded FOX and poly gate structure, for effectively reducing the trigger voltage of a conventional field device, for improving the robustness of a NMOS transistor of a small drive I/O circuit, and for improving the ESD performance of a stack-gate voltage tolerant I/O.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: August 14, 2007
    Assignee: Winbond Electronics Corp.
    Inventors: Shi-Tron Lin, Wei-Fan Chen
  • Patent number: 7253500
    Abstract: A semiconductor wafer includes (a) a first principal side and a second principal side opposite to each other, (b) a first bevel contour and a second bevel contour provided at an outer periphery of the first principal side and the second principal side, (c) a first recess formed in the first bevel contour, and (d) a first type of ID mark configured by a protruding dot provided on a bottom face of the first recess.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: August 7, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masao Iwase, Soichi Nadahara
  • Patent number: 7253491
    Abstract: A silicon light-receiving device is provided. In the device, a substrate is based on n-type or p-type silicon. A doped region is ultra-shallowly doped with the opposite type dopant to the dopant type of the substrate on one side of the substrate so that a photoelectric conversion effect for light in a wavelength range of 100-1100 nm is generated by a quantum confinement effect in the p-n junction with the substrate. First and second electrodes are formed on the substrate so as to be electrically connected to the doped region. Due to the ultra-shallow doped region on the silicon substrate, a quantum confinement effect is generated in the p-n junction. Even though silicon is used as a semiconductor material, the quantum efficiency of the silicon light-receiving device is far higher than that of a conventional solar cell, owing to the quantum confinement effect. The silicon light-receiving device can also be formed to absorb light in a particular or large wavelength band, and used as a solar cell.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: August 7, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Kyung Lee, Byoung-Lyong Choi, Jun-Young Kim
  • Patent number: 7253508
    Abstract: A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed “?”-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Liu, Hsueh-Te Wang, Meng-Jen Wang, Chi-Hao Chiu, Tai-Yuan Huang
  • Patent number: 7253015
    Abstract: A repeatable and uniform low doped layer is formed using modulation doping by forming alternating sub-layers of doped and undoped nitride semiconductor material atop another layer. A Schottky diode is formed of such a low doped nitride semiconductor layer disposed atop a much more highly doped nitride semiconductor layer. The resulting device has both a low on-resistance when the device is forward biased and a high breakdown voltage when the device is reverse biased.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: August 7, 2007
    Assignee: Velox Semiconductor Corporation
    Inventors: Milan Pophristic, Michael Murphy, Richard A. Stall, Bryan S. Shelton, Linlin Liu, Alex D. Ceruzzi
  • Patent number: 7253486
    Abstract: In one example embodiment, a transistor (100) is provided. The transistor (100) comprises a source (10), a gate (30), a drain (20), and a field plate (40) located between the gate (30) and the drain (20). The field plate (40) comprises a plurality of connection locations (47) and a plurality of electrical connectors (45) connecting said plurality of connection locations (47) to a potential.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: August 7, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Bruce M. Green, Ellen Lan, Phillip Li
  • Patent number: 7253431
    Abstract: A method is provided for doping a carbon nanotube. The method comprises exposing the nanotube to a one-electron oxidant in a solution phase. A method is also provided for forming a carbon nanotube FET device.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: August 7, 2007
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Phaedon Avouris, Jia Chen, Christian Klinke, Paul M. Solomon