Abstract: Systems using coded particles for multiplexed analysis of biological samples or reagents, in which the codes on the particles are at least partially defined by light-polarizing materials.

Abstract: Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed within the epitaxial layer to expose the first source; a floating gate device formed inside the opening; and a select gate device formed on the epitaxial layer at a distance from the floating gate device.

Abstract: The silicon-on-insulator (SOI) arrangement provides dual SOI film thicknesses for body-resistance control and provides a bulk silicon substrate on which a buried oxide (BOX) layer is provided. The BOX layer has recesses formed therein and unrecessed portions. The silicon layer is formed on the BOX layer and closes the recesses and covers the unrecessed portions of the BOX layer. Shallow trench isolation regions define and isolate first silicon regions from second silicon regions that each include one of the recesses. Floating-body devices are formed within the first silicon regions, which exhibit a first thickness, and body-tied devices are formed within the second silicon regions that include the thicker silicon of the recesses.

Abstract: The present invention relates to a battery mounted integrated circuit device where an integrated circuit and a solid state battery are formed on the same substrate. In this battery mounted integrated circuit device, a first diffusion layer containing an N-type impurity is formed between a region of a semiconductor substrate where the solid state battery is mounted and a region of the semiconductor substrate where the integrated circuit is mounted, and a second diffusion layer containing an N-type impurity is formed below the region of the semiconductor substrate where the solid state battery is mounted, and overlaps with the first diffusion layer.

Abstract: The semiconductor device comprises a lower interconnection part 12 which is formed on a silicon substrate 10 and includes an inter-layer insulation film 36 formed of a low-k film 32 and a hydrophilic insulation film 34 formed on the low-k film 32, and an interconnection layer 44a, 44b buried in interconnection trenches 38a, 38b formed in the inter-layer insulation film 36 and having an interconnection pitch which is a first pitch; and an intermediate interconnection part 14 which is formed on the lower interconnection part 12 and includes an inter-layer insulation film 142 formed of low-k films 136, 140, an interconnection layer 152a, 152b buried in interconnection trenches 146a, 146b formed in the inter-layer insulation film 142 and having an interconnection pitch which is a second pitch larger than the first pitch, and an SiC film 154 formed directly on the low-k film 140 and the interconnection layer 152a, 152b.

Abstract: A method of forming a layer of silicon carbide wherein silicon clusters are dissociated in a gas phase. Silicon clusters may be dissociated by a silicon-etching gas such as a group VII-containing component. A semiconductor device is also disclosed having a layer formed by the methods of the invention.

Abstract: A semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having such a composition as to generate a 2-dimensional electron gas layer in the upper portion of the first nitride semiconductor layer, and an electrode having an ohmic property and formed selectively on the second nitride semiconductor layer. The second nitride semiconductor layer includes a contact area having at least one inclined portion with a bottom or wall surface thereof being inclined toward the upper surface of the first nitride semiconductor layer and defining a depressed cross-sectional configuration. The electrode is formed on the contact area.

Abstract: An interposer for use in an external lead or land pattern semiconductor package. The interposer includes an interposer body which is molded from a dielectric material. The interposer body defines opposed top and bottom surfaces, an outer peripheral edge, and an inner peripheral edge. Embedded within the interposer body is a die pad which itself defines opposed top and bottom surfaces and a peripheral edge. The bottom surface of the die pad is exposed in and substantially flush with the bottom surface of the interposer body, with the inner peripheral edge of the interposer body and the top surface of the die pad collectively defining a cavity of the interposer. A plurality of electrically conductive interposer leads are embedded within the top surface of the interposer body and at least partially exposed therein. The interposer body forms a nonconductive barrier between each of the interposer leads and between the interposer leads and the die pad.

Abstract: The present invention is a semiconductor module (20) in which, for example, twenty-five semiconductor devices (10) with a pnotoelectric conversion function are arranged in the form of a five row by five column matrix via an electrically conductive mechanism including of six connecting leads (21 to 26). The semiconductor devices (10) in each column are connected in series, and the semiconductor devices (10) in each row are connected in parallel. Positive and negative terminals, which are embedded in a light transmitting member (28) made of a transparent synthetic resin and which protrude to the outside, are also provided. The semiconductor device (10) comprises a diffusion layer, a pn junction, and one flat surface on the surface of a spherical p-type semiconductor crystal, for example.

Abstract: A technique for and structures for camouflaging an integrated circuit structure. The technique including forming active areas of a first conductivity type and LDD regions of a second conductivity type resulting in a transistor that is always non-operational when standard voltages are applied to the device.

Abstract: An n-type InP sub collector layer 2 heavily doped with silicon (Si), an InP collector layer 3, a p-type GaAs(0.51)Sb(0.49) base layer 4 heavily doped with carbon (C), an n-type In(1-y)Al(y)P emitter layer 7 doped with Si, an n-type InP cap layer 8 heavily doped with Si, and an n-type In(0.53)Ga(0.47)As contact layer 9 heavily doped with Si are stacked on a substrate 1.

Abstract: A method of manufacturing a data carrier from a support strip includes an overmoulding step, in which at least one support element of the support strip is overmoulded so as to obtain a data carrier body, and a microcircuit-connecting step, in which a microcircuit is electrically connected to the wiring pads of the data carrier body so as to obtain the data carrier.

Abstract: A pressure sensor includes a sensor chip and a circuit chip. The sensor chip, which is configured to generate an electrical signal representative of a pressure being sensed, has a surface including a sensing area and a plurality of electrical contact pads disposed on the surface. The circuit chip includes a circuit configured to process the electrical signal and has a surface on which a plurality of electrical contact pads of the circuit chip are disposed. The circuit chip is joined to the sensor chip so that the electrical contact pads of the circuit chip are respectively electrically connected to those of the sensor chip, all the electrical contact pads of the circuit chip and the sensor chip are hermetically sealed and isolated from the fluid, and the surfaces of the circuit chip and the sensor chip face each other with the electrical contact pads of the same interposed therebetween.

Abstract: A method for reducing the parasitic capacitance in resistors, and a resistor design embodying this method are described. By creating a p-type or an n-type implant inside of an n-well or a p-substrate, respectively, where the n-well or p-substrate is located in a p-substrate or n-substrate, respectively, a capacitively coupled capacitor is formed in series connection with the parasitic inter-layer dielectric capacitance generated when the resistor is fabricated in the dielectric material. The depletion region formed thereby behaves as a series capacitor which reduces the overall capacitance of the assemblage. The n-well or p-substrate can be placed in electrical connection with a ground potential or brought to a chosen voltage to further increase the depletion region and reduce the capacitance of the resistor.

Abstract: When the scribe region 2 is cut off, the dicing detector 53 sends the detection signal A to the changeover circuit 51 and electrically shuts off the pad 50 and the inspection objective circuit 52, and the fixed potential of the input and output passage 54 from the changeover circuit 51 to the inspection objective circuit 52 is monitored by the detector 55. At the same time, the detection objective circuit 52 is changed into a mode, in which a reception of the command of the inspection mode is refused, by the detection signal A. In the case where an abnormality of the fixed potential of the input and output passage 54 is grasped, the inspection objective circuit 52 is changed into the safety mode.

Abstract: By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be reduced or avoided. The resistive film may be sufficiently resistive that it heats the phase change material and causes the appropriate phase transitions without requiring a dielectric breakdown of the phase change material.

Abstract: A method for forming a volatile memory device. A substrate comprising a pair of neighboring trenches is provided, each trench comprising a capacitor. A collar insulating layer is formed on an upper sidewall of each trench. The collar insulating layer comprises a low level portion and a high level portion adjacent to a predetermined active area of the volatile memory device.

Abstract: A silicide film is provided in diffusion regions formed in a semiconductor layer. The silicide film has a thickness substantially same as that of the semiconductor layer. The silicide film has the bottom located in the vicinity of an interface between the insulator film and the semiconductor layer.

Abstract: A lead frame structure includes: at least a die pad for mounting a semiconductor chip thereon; a plurality of suspension members mechanically connected with the die pad; and a plurality of supporting members. Each supporting member has a connection region mechanically connected with each of the plurality of suspension members for mechanically supporting the at least die pad via the plurality of suspension pins. The connection region of the supporting member has a penetrating opening portion which provides a mechanical flexibility to the connection region and which allows the connection region to be deformed toward the suspension member upon application of a tensile stress to the suspension member in a down-set process.

Abstract: By securing a fatigue life of a connection portion with a semiconductor package and a mount board, a semiconductor device having a high reliability is provided. The semiconductor device consists of a semiconductor element, a mount board in which said semiconductor element is mounted, and a support member in which said mount board is supported through a connection member, wherein the connection member consists of a first mount board connection portion with the mount board at a first side of the element in a direction along a main surface of the mount board in which the semiconductor element is mounted, and consists of a first support member connection portion with the support member at a second side in opposition to the first side through the semiconductor element.