Patents Examined by Sarah Salerno
  • Patent number: 10283363
    Abstract: A quasi-vertical Schottky diode architecture includes a topside anode contact that connects to external circuitry through an airbridge finger, a thin mesa of semiconductor material with epilayers including a bottomside highly-doped layer, a bottomside ohmic contact directly below the anode, and a host substrate onto which the diode material is bonded by a thin adhesive layer. A method of fabricating the diode architecture includes preparation of the semiconductor wafer for processing (including initial etching to expose the highly-doped epilayer, deposition of metals and annealing to form the ohmic contact, application of the adhesive layer to the host substrate, thermal compression bonding of diode wafer and host wafer, with ohmic contact side facing host wafer to form a composite wafer, etching and formation of diode mesas to isolate devices on the host substrate, lithography and formation of topside anode contact and external circuitry on host wafer).
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: May 7, 2019
    Assignee: UNIVERSITY OF VIRGINIA PATENT FOUNDATION
    Inventors: Naser Alijabbari, Robert M. Weikle, II, Matthew Bauwens
  • Patent number: 10222272
    Abstract: In one embodiment, a semiconductor device (20) includes a semiconductor chip (200) in which functional blocks (201, 202, 203 etc.) and a temperature sensor (208) are integrated. In this embodiment, in response to a change in an operation state of the semiconductor device (20), the on-chip temperature sensor (208) operates to switch from a continuous operation in which it continuously measures a chip temperature to an intermittent operation in which it intermittently measures the chip temperature, or to change a time interval between intermittent measurements of the chip temperature.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Chiaki Kumahara, Akira Tsurugasaki
  • Patent number: 10217739
    Abstract: A bipolar junction transistor having a relatively reduced size and an improved current gain and a method of manufacturing the same are disclosed. The bipolar junction transistor includes a plurality of emitter regions disposed in a substrate, a plurality of base regions disposed in the substrate and configured to surround the emitter regions, respectively, and a collector region disposed in the substrate and configured to surround the base regions. The plurality of emitter and base regions may be arranged in a matrix.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: February 26, 2019
    Assignee: DB Hitek Co., Ltd
    Inventor: Joo Hyung Kim
  • Patent number: 10211242
    Abstract: An image sensor is provided. The image sensor includes a visible light receiving portion and an infrared receiving portion. The visible light receiving portion is configured to receive a visible light. The infrared receiving portion is configured to receive infrared. The visible light receiving portion comprises an infrared cutoff filter, plural primary color filters, and plural secondary color filters. The primary color filters and the secondary color filters are disposed on the infrared cutoff filter. The infrared receiving portion comprises plural first infrared pass filters and plural second infrared pass filters disposed on the first infrared pass filters. Each of the primary color filters occupies a first area. The secondary color filters and the second infrared pass filters occupy a second area substantially equal to the first area.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: February 19, 2019
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Yu-Jui Hsieh, Po-Nan Chen
  • Patent number: 10204871
    Abstract: Provided is a semiconductor device including an insulating plate; a first conducting portion formed on a first surface of the insulating plate; a semiconductor element mounted on the first conducting portion; and a mold material that seals the first conducting portion and the semiconductor element on the first surface side of the insulating plate. A material of the insulating plate has higher adhesion with respect to the mold material than a material of the first conducting portion, and the first conducting portion includes a gap that is filled with the mold material between the first conducting portion and the insulating plate in a portion thereof.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: February 12, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yuichiro Hinata
  • Patent number: 10204860
    Abstract: A method for forming a semiconductor structure includes forming a first metal layer over a first dielectric layer, forming a first graphene layer on at least one major surface of the first metal layer, and forming a second dielectric layer over the first metal layer and the first graphene layer. The method further includes forming an opening in the second dielectric layer which exposes the first metal layer, forming a second metal layer over the second dielectric layer and within the opening, and forming a second graphene layer on at least one major surface of the second metal layer, wherein the second graphene layer is also formed within the opening.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: February 12, 2019
    Assignee: NXP USA, Inc.
    Inventors: Douglas M. Reber, Mehul D. Shroff
  • Patent number: 10186682
    Abstract: To realize a high-performance liquid crystal display device or light-emitting element using a plastic film. A CPU is formed over a first glass substrate and then, separated from the first substrate. A pixel portion having a light-emitting element is formed over a second glass substrate, and then, separated from the second substrate. The both are bonded to each other. Therefore, high integration can be achieved. Further, in this case, the separated layer including the CPU serves also as a sealing layer of the light-emitting element.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: January 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Patent number: 10186516
    Abstract: A one time programmable (OTP) memory device, a method of manufacturing the same, and an electronic device including the same, which lower a programming voltage to enhance programming efficiency, increase reliability of peripheral input/output (I/O) elements used for a design of the OTP memory device, and simplify the design, are provided. The OTP memory device includes a transistor including one of a first gate structure including a high-k dielectric layer, a rare earth element (RE) supply layer, and a second metal layer, a second gate structure including the high-k dielectric layer, a first metal layer, and the second metal layer, and a third gate structure including the high-k dielectric layer and the second metal layer.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: January 22, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-jung Jin, Sang-woo Pae, Hyun-min Choi
  • Patent number: 10181508
    Abstract: Provided is a guard ring section to which a fine processing is easily applied. Provided is a semiconductor device comprising: a semiconductor substrate; an active region formed in the semiconductor substrate; and a guard ring section formed more outside than the active region in the semiconductor substrate, wherein the guard ring section includes: a guard ring formed in a circular pattern on an upper surface of the semiconductor substrate; an interlayer insulating film formed above the guard ring; a field plate formed in a circular pattern along the guard ring and above the interlayer insulating film; and a tungsten plug formed in a circular pattern along the guard ring and penetrating the interlayer insulating film to connect the guard ring and the field plate.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: January 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroyuki Tanaka, Kota Ohi, Yuichi Onozawa, Yoshihiro Ikura, Kazutoshi Sugimura
  • Patent number: 10177152
    Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
  • Patent number: 10177093
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo-Jin Kim, Chang-Hwa Kim, Hwi-Chan Jun, Chul-Hong Park, Jae-Seok Yang, Kwan-Young Chun
  • Patent number: 10164177
    Abstract: A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. A first portion of a magnetoresistive stack corresponding to the magnetic junction is provided. Providing this portion of the magnetoresistive stack includes providing at least one layer for a free layer of the magnetic junction. A second portion of the magnetoresistive stack is provided after the step of providing the first portion of the magnetoresistive stack. The magnetoresistive stack is patterned to provide the magnetic junction after the step of providing the second portion of the magnetoresistive stack. An ambient temperature for the magnetoresistive stack and the magnetic junction does not exceed a crystallization temperature of the free layer after the step of providing the free layer through the step of patterning the magnetoresistive stack.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sebastian Schafer, Dmytro Apalkov, Vladimir Nikitin, Don Koun Lee
  • Patent number: 10164003
    Abstract: A method of forming a metal-insulator-metal capacitor is provided. The method includes forming a first metal plate over a semiconductor substrate, forming a first dielectric layer with a first dielectric constant on a surface of the first metal plate, forming a second dielectric layer with a second dielectric constant on a surface of the first dielectric layer, forming a third dielectric layer with a third dielectric constant on a surface of the second dielectric layer, and forming a second metal plate on a surface of the third dielectric layer. The second dielectric constant is different from the first dielectric constant and different from the third dielectric constant.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsing-Lien Lin, Hai-Dang Trinh, Cheng-Yuan Tsai
  • Patent number: 10141359
    Abstract: An image sensor is provided. The image sensor includes an infrared receiving portion and a visible light receiving portion. The infrared receiving portion is configured to receive infrared. The visible light receiving portion is configured to receive a visible light. The visible light receiving portion includes an infrared cutoff filter grid configured to purify the visible light.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: November 27, 2018
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Yu-Jui Hsieh, Po-Nan Chen
  • Patent number: 10141233
    Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: November 27, 2018
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Lu-Yi Chen, Chang-Lun Lu
  • Patent number: 10121752
    Abstract: A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed characteristics, such as compliance and electro-migration resistance, of the interlayer structure may be satisfied by different material layers, rather attempting to achieve these characteristics with a single layer. In one embodiment, the multilayer interlayer structure may comprises a two-layer structure, wherein a first layer is formed proximate a solder interconnect and comprises a material which forms a ductile joint with the solder interconnect, and a second layer comprising a material having strong electro-migration resistance formed between the first layer and an interconnection pad. In a further embodiment, third layer may be formed adjacent the interconnection pad comprising a material which forms a ductile joint with the interconnection pad.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Kyu Oh Lee
  • Patent number: 10096490
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 9, 2018
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 10090194
    Abstract: A method of manufacturing a semiconductor device includes the step of positioning a patterned mask over a dielectric layer. The dielectric layer comprises a low-temperature cure polyimide. The method further includes the steps of exposing a first surface of the dielectric layer through the patterned mask to an I-line wavelength within an I-line stepper, and developing the dielectric layer to form an opening.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 10062759
    Abstract: A MOSFET using a SiC substrate has a problem that a carbon-excess layer is formed on a surface by the application of mechanical stress due to thermal oxidation and the carbon-excess layer degrades mobility of channel carriers. In the invention, (1) a layer containing carbon-carbon bonds is removed; (2) a gate insulating film is formed by a deposition method; and (3) an interface between a crystal surface and the insulating film is subjected to an interface treatment at a low temperature for a short time. Due to this, the carbon-excess layer causing characteristic degradation is effectively eliminated, and at the same time, dangling bonds can be effectively eliminated by subjecting an oxide film and an oxynitride film to an interface treatment.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: August 28, 2018
    Assignee: HITACHI, LTD.
    Inventors: Digh Hisamoto, Keisuke Kobayashi, Naoki Tega, Toshiyuki Ohno, Hirotaka Hamamura, Mieko Matsumura
  • Patent number: 10043708
    Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: August 7, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Viraj Sardesai, Suraj K. Patil, Scott Beasor, Vimal Kumar Kamineni