Abstract: A semiconductor manufacturing tool and process to form semiconductor devices is provided. An edge ring of the semiconductor manufacturing tool comprises a high electron mobility material in order to extend an electrical field and sheath such that curvature from the sheath is moved away from a semiconductor wafer so that an impact from the curvature is reduced or eliminated during an etching process.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.

Abstract: One illustrative integrated circuit product disclosed herein includes a first final gate structure, a second final gate structure and an insulating gate separation structure positioned between the first and second final gate structures. In this example, the insulating gate separation structure comprises an upper portion and a lower portion. The lower portion has a first lateral width in a first direction that is substantially uniform throughout a vertical height of the lower portion. The upper portion has a substantially uniform second lateral width in the first direction that is substantially uniform throughout a vertical height of the upper portion, wherein the second lateral width is less than the first lateral width.

Abstract: An embodiment method of forming a package-on-package (PoP) device includes temporarily mounting a substrate on a carrier, stacking a first die on the substrate, at least one of the die and the substrate having a coefficient of thermal expansion mismatch relative to the carrier, and stacking a second die on the first die. The substrate may be formed from one of an organic substrate, a ceramic substrate, a silicon substrate, a glass substrate, and a laminate substrate.

Abstract: Semiconductor layer 110 is formed on semiconductor substrate 101. Semiconductor layer 110 has a plurality of well regions 103 in a surface remote from semiconductor substrate 101. Semiconductor layer 110 includes drift region 102 in addition to the plurality of well regions 103. The plurality of well regions 103 each include body region 105, source region 108, and contact region 109. Source region 108 is in contact with body region 105. Contact region 109 is in contact with both body region 105 and source region 108. Body region 105, source region 108, and source wire 118 are at an identical potential because of contact region 109. Semiconductor layer 110 includes ineffective region R at the surface remote from semiconductor substrate 101.

Abstract: There is disclosed a method of preparing a photovoltaic device. In particular, the method comprises making thin-film GaAs solar cells integrated with low-cost, thermoformed, lightweight and wide acceptance angle mini-CPCs. The fabrication combines ND-ELO thin film cells that are cold-welded to a foil substrate, and subsequently attached to the CPCs in an adhesive-free transfer printing process. There is also disclosed an improved photovoltaic device made by the disclosed method. The improved photovoltaic device comprises a thin-film solar integrated with non-tracking mini-compound parabolic concentrators, wherein the plastic compound parabolic concentrator comprise two parabolas tilted at an angle equal to the acceptance angle of the compound parabolic concentrator.

Abstract: A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. The asymmetric spacer assembly is formed by a self-aligned process, resulting in less gate/junction overlap on the drain side of the device and greater gate/junction overlap on the source side of the device. Asymmetric transistors having small gate lengths can be obtained without overlay/misalignment issues.

Abstract: A memory transistor includes a gate electrode and a blocking structure disposed beneath the gate electrode, where the blocking structure is formed by plasma oxidation. The memory transistor includes a multi-layer charge storage layer disposed beneath the blocking structure, wherein the multi-layer charge storage layer includes a trap dense charge storage layer over a substantially trap free charge storage layer, where a thickness of the trap dense charge storage layer is reduced by the plasm oxidation. The memory transistor further includes a tunneling layer disposed beneath the multi-layer charge storage layer and a channel region disposed beneath the tunneling layer, where the channel region is positioned laterally between a source region and a drain region.

Abstract: The present invention provides a method to manufacture nanowires. In various embodiments, a method is provided for producing an oxidized non-zinc metal layer as a heterogeneous seed layer on arbitrary substrate for controlled nanowire growth is disclosed which comprises depositing a metal layer at low temperature on a substrate, oxidizing the metal layer in air ambient or in oxidizing agent, and growing nanowires at low temperatures on oxidized metal layers on virtually any substrate.

Abstract: Over a front surface of a silicon semiconductor wafer is deposited a high dielectric constant film with a silicon oxide film, serving as an interface layer, provided between the semiconductor wafer and the high dielectric constant film. After a chamber houses the semiconductor wafer, a chamber's pressure is reduced to be lower than atmospheric pressure. Subsequently, a gaseous mixture of ammonia and nitrogen gas is supplied into the chamber to return the pressure to ordinary pressure, and the front surface is irradiated with a flash light, thereby performing post deposition annealing (PDA) on the high dielectric constant film. Since the pressure is reduced once to be lower than atmospheric pressure and then returned to ordinary pressure, a chamber's oxygen concentration is lowered remarkably during the PDA. This restricts an increase in thickness of the silicon oxide film underlying the high dielectric constant film by oxygen taken in during the PDA.

Abstract: In order to remove from a substrate having a concavo-convex pattern formed on a surface of the substrate, a solid material with which a concave portion of the concavo-convex pattern is filled and which is formed by evaporating a solvent in a sublimable substance solution containing a sublimable substance that sublimates at a temperature equal to or higher than a first temperature, and an impurity that evaporates at a temperature equal to or higher than a second temperature that is higher than the first temperature, the prevent invention provides a substrate processing apparatus and a substrate processing method which heat the substrate to a temperature equal to or higher than the second temperature.

Abstract: A method is provided that includes forming a dielectric material and a first sacrificial material above a substrate, forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material, forming a first hole in the second sacrificial material, the first hole disposed in a first direction, forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole, forming a second hole in the second sacrificial material, forming a second portion of the nonvolatile memory material on a sidewall of the second hole, forming a local bit line in the second hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.

Abstract: The present disclosure relates to an integrated circuit module with electromagnetic shielding. The integrated circuit module includes a die with an input/output (I/O) port at a bottom surface of the die, a mold compound partially encapsulating the die and leaving the bottom surface of the die exposed, a first dielectric pattern over the bottom surface of the die, a redistribution structure over the first dielectric pattern, and a shielding structure. The I/O port at the bottom surface of the die is exposed through the first dielectric pattern. The redistribution structure includes a shield connected element that is coupled to the I/O port and extends laterally beyond the die. The shielding structure resides over a top surface of the mold compound, extends along side surfaces of the mold compound, and is in contact with the shield connected element. Herein, the shielding structure does not extend vertically beyond the shield connected element.

Abstract: A process of producing a component includes providing a substrate having an electrically conductive surface in the form of an electrically conductive layer; subdividing the layer with the aid of a laser process into a first electrically autonomous region and a second electrically autonomous region, wherein an electrically insulating region is formed in the electrically conductive layer to electrically separate the electrically autonomous regions; forming an electrical potential difference between the first electrically autonomous region and the second electrically autonomous region; and applying an electrically charged substance or an electrically charged substance mixture onto the first electrically autonomous region and/or the second electrically autonomous region, wherein the electrically autonomous region and/or an amount of the applied electrically charged substance or of the electrically charged substance mixture are adjusted by the electrical potential difference.

Abstract: There is provided a method of manufacturing a semiconductor device, which includes: forming a seed layer doped with a dopant on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a halogen-based first process gas to the substrate, supplying a non-halogen-based second process gas to the substrate, and supplying a dopant gas to the substrate; and supplying a third process gas to the substrate to form a film on the seed layer.

Abstract: A process of producing a component includes providing a substrate having an electrically conductive surface in the form of an electrically conductive layer; subdividing the layer with the aid of a scratching process into a first electrically autonomous region and a second electrically autonomous region, wherein an electrically insulating region is formed in the electrically conductive layer to electrically separate the electrically autonomous regions; forming an electrical potential difference between the first electrically autonomous region and the second electrically autonomous region; and applying an electrically charged substance or an electrically charged substance mixture onto the first electrically autonomous region and/or the second electrically autonomous region, wherein the electrically autonomous region and/or an amount of the applied electrically charged substance or of the electrically charged substance mixture are adjusted by the electrical potential difference.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a target layer over a substrate and forming a seed layer over the target layer. The method includes forming a hard mask layer over the seed layer, and the hard mask layer includes an opening to expose a portion of the seed layer. The method includes forming a conductive layer in the opening, and the conductive layer is selectively formed on the portion of the seed layer. The method includes etching a portion of the target layer by using the conductive layer as a mask.

Abstract: At least one method, apparatus and system disclosed involves providing an integrated circuit having metal feature flyover over an middle-of-line (MOL) feature. A first location for a non-contact intersection region between a first middle of line (MOL) interconnect feature and a metal feature in a functional cell is determined. A dielectric feature is formed over the first MOL interconnect feature at the first location. The metal feature is formed over the dielectric layer, the dielectric layer providing a predetermined amount of voltage isolation between the first MOL interconnect feature and the metal feature.

Abstract: Methods of doping semiconductor substrates using deposition of a rare earth metal-containing film such as an yttrium-containing film, and annealing techniques are provided herein. Rare earth metal-containing films are deposited using gas, liquid, or solid precursors without a bias and may be deposited conformally. Some embodiments may involve deposition using a plasma. Substrates may be annealed at temperatures less than about 500° C.

Abstract: A method is presented for forming a semiconductor structure. The method includes forming a fin structure over a substrate, forming a dummy gate over the fin structure, and etching the dummy gate by a first amount to expose a top portion of the fin structure. The method further includes forming a first dielectric layer adjacent the exposed top portion of the fin structure, forming a spacer adjacent the first dielectric layer contacting the fin structure, and etching the dummy gate by a second amount. The method further includes depositing a second dielectric layer to encapsulate the remaining dummy gate, depositing an inter-level dielectric (ILD) over the second dielectric layer, depositing at least one hard mask to access the dummy gate, stripping the dummy gate to form at least one recess, and filling the at least one recess with a high-k metal gate (HKMG).