Patents Examined by Scott B. Geyer
  • Patent number: 11749781
    Abstract: A light emitting device including a first light emitting part including a first n-type semiconductor layer, a first active layer, a first p-type semiconductor layer, and a first transparent electrode, a second light emitting part disposed over the first light emitting part and including a second n-type semiconductor layer, a second active layer, a second p-type semiconductor layer, and a second transparent electrode, and a third light emitting part disposed over the second light emitting part and including a third n-type semiconductor layer, a third active layer, a third p-type semiconductor layer, and a third transparent electrode, in which the light emitting device has substantially a quadrangular shape when viewed from the top, and has first to fourth corners, and a length between first and second corners of the third light emitting part is less than a length between third and fourth corners of the third light emitting part.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: September 5, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Chang Yeon Kim
  • Patent number: 11735608
    Abstract: An imaging apparatus includes: a semiconductor substrate which includes a charge accumulation portion containing an impurity of a first conductivity type; a contact plug which is connected to the charge accumulation portion, contains an impurity of the first conductivity type, and is not silicide; a first insulating film which includes an upper wall located above the contact plug; and a second insulating film which includes a portion located above the upper wall. A material of the second insulating film is different from a material of the first insulating film, and the first insulating film is thinner than the second insulating film.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: August 22, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Kosaku Saeki
  • Patent number: 11735495
    Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. Fluid conduits may be at least partially defined by an interconnect trace comprising a metal. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Omkar Karhade, Mitul Modi, Edvin Cetegen, Aastha Uppal
  • Patent number: 11728397
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes an inter-level dielectric layer. A first contact that includes a fill material is formed that extends through the inter-level dielectric layer. The inter-level dielectric layer is recessed such that the fill material extends above a top surface of the inter-level dielectric layer. An etch-stop layer is formed on the inter-level dielectric layer such that the fill material of the first contact extends into the etch-stop layer. A second contact is formed extending through the etch-stop layer to couple to the first contact. In some such examples, the second contact physically contacts a top surface and a side surface of the first contact.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Hung Tsai, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11728299
    Abstract: The present disclosure relates to a semiconductor device with tilted insulating layers and a method for fabricating the semiconductor device with the tilted insulating layers. The semiconductor device includes a substrate, two conductive pillars positioned above the substrate and extended along a vertical axis, a first set of tilted insulating layers parallel to each other and positioned between the two conductive pillars, and a second set of tilted insulating layers parallel to each other and positioned between the two conductive pillars. The first set of tilted insulating layers are extended along a first direction slanted with respect to the vertical axis, the second set of tilted insulating layers are extended along a second direction slanted with respect to the vertical axis, and the first direction and the second direction are crossed.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: August 15, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11721493
    Abstract: A liquid dispersion composition for solid electrolytic capacitor production, containing a conjugated conductive polymer prepared by polymerizing a monomer compound in a dispersion medium containing seed particles with protective colloid formed of a polyanion or in a dispersion medium containing a polyanion, and a compound (a) represented by a general formula (1), where R1 to R6 and k are as defined in the description; and a method for producing a solid electrolytic capacitor, including a step of adhering the composition to a porous anode body made of a valve action metal having a dielectric coating film on the surface thereof, and a step of removing the dispersion medium from the liquid dispersion composition having adhered to the porous anode body to form a solid electrolyte layer
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: August 8, 2023
    Assignee: SHOWA DENKO K.K.
    Inventors: Takeshi Kawamoto, Takashi Okubo
  • Patent number: 11715721
    Abstract: Disclosed herein is an electrical connecting structure having nano-twins copper, including a first substrate having a first nano-twins copper layer and a second substrate having a second nano-twins copper layer. The first nano-twins copper layer includes a plurality of first nano-twins copper grains. The second nano-twins copper layer includes a plurality of second nano-twins copper grains. The first nano-twins copper layer is joined with the second nano-twins copper layer. At least a portion of the first nano-twins copper grains extend into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains extend into the first nano-twins copper layer.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 1, 2023
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Chih Chen, Kai-Cheng Shie, Jing-Ye Juang
  • Patent number: 11710788
    Abstract: A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: July 25, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyujin Kim, Hui-Jung Kim, Junsoo Kim, Sangho Lee, Jae-Hwan Cho, Yoosang Hwang
  • Patent number: 11711892
    Abstract: A thin, flexible computerized sensing platform which can be affixed to a structure to be sensed, which has excellent mechanical coupling between the sensors and the object to be sensed, which can be self-powered and rechargeable, and which can be environmentally sealed, and a method for assembling and utilizing the same.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 25, 2023
    Assignee: Velvetwire LLC
    Inventors: Eric Oleg Bodnar, Jacob Van Reenen Pretorius
  • Patent number: 11707000
    Abstract: A quantum device is fabricated by forming a network of nanowires oriented in a plane of a substrate to produce a Majorana-based topological qubit. The nanowires are formed from combinations of selective-area-grown semiconductor material along with regions of a superconducting material. The selective-area-grown semiconductor material is grown by etching trenches to define the nanowires and depositing the semiconductor material in the trenches. A side gate is formed in an etched trench and situated to control a topological segment of the qubit.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 18, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dmitry Pikulin, Michael H. Freedman, Roman Lutchyn, Peter Krogstrup Jeppesen, Parsa Bonderson
  • Patent number: 11705391
    Abstract: An interposer includes: a base substrate; an interconnection structure on a top surface of the base substrate and including a metal interconnection pattern; an upper passivation layer on the interconnection structure and having compressive stress; a lower passivation layer under a bottom surface of base substrate, the lower passivation layer having compressive stress that is less than the compressive stress of the upper passivation layer; a lower conductive layer under the lower passivation layer; and a through electrode penetrating the base substrate and the lower passivation layer. The through electrode electrically connects the lower conductive layer to the metal interconnection pattern of the interconnection structure.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: July 18, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yu-Kyung Park, Seung-kwan Ryu, Min-seung Yoon, Yun-seok Choi
  • Patent number: 11705448
    Abstract: A number of monolithic diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a method of manufacture of a monolithic diode limiter includes providing an N-type semiconductor substrate, providing an intrinsic layer on the N-type semiconductor substrate, implanting a first P-type region to a first depth into the intrinsic layer, implanting a second P-type region to a second depth into the intrinsic layer, and forming at least one passive circuit element over the intrinsic layer. The method can also include forming an insulating layer on the intrinsic layer, forming a first opening in the insulating layer, and forming a second opening in the insulating layer. The method can also include implanting the first P-type region through the first opening and implanting the second P-type region through the second opening.
    Type: Grant
    Filed: July 13, 2021
    Date of Patent: July 18, 2023
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: James Joseph Brogle, Joseph Gerard Bukowski, Margaret Mary Barter, Timothy Edward Boles
  • Patent number: 11696516
    Abstract: Various embodiments of a modular unit for a topologic qubit and of scalable quantum computing architectures using such modular units are disclosed herein. For example, one example embodiment is a modular unit for a topological qubit comprising 6 Majorana zero modes (MZMs) on a mesoscopic superconducting island. These units can provide the computational MZMs with protection from quasiparticle poisoning. Several possible realizations of these modular units are described herein. Also disclosed herein are example designs for scalable quantum computing architectures comprising the modular units together with gates and reference arms (e.g., quantum dots, Majorana wires, etc.) configured to enable joint parity measurements to be performed for various combinations of two or four MZMs associated with one or two modular units, as well as other operations on the states of MZMs.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: July 4, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Michael Freedman, Chetan Nayak, Roman Lutchyn, Torsten Karzig, Parsa Bonderson
  • Patent number: 11674077
    Abstract: A process for the post-deposition treatment of colloidal quantum dot films to improve photodetector performance. A colloidal quantum dot film is first deposited on a suitable substrate or device structure, given a ligand exchange, and then allowed to dry into a completed film. Next, a solution is prepared consisting of dilute H2O2 mixed with a polar solvent such as isopropyl alcohol solution. The prepared film and substrate are then immersed into the prepared solution over a set interval of time. After which, the film is removed and rinsed with solvent, then dried with clean N2 gas. After this treatment, the colloidal quantum dot film is ready for use as a photodetector.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: June 13, 2023
    Assignee: Sivananthan Laboratories, Inc.
    Inventors: Anthony Joseph Ciani, Richard Edward Pimpinella, Christopher Frank Buurma, Jered Feldman, Christoph H. Grein
  • Patent number: 11677011
    Abstract: A method of fabricating transistors with a vertical gate in trenches includes lithographing to form wide trenches; forming dielectric in the trenches and filling the trenches with flowable material; and lithography to form narrow trenches within the wide trenches thereby exposing well or substrate before epitaxially growing semiconductor strips atop substrate exposed by the narrow trenches; removing the flowable material; growing gate oxide on the semiconductor strip; forming gate conductor over the gate oxide and into gaps between the epitaxially-grown semiconductor strips and the dielectric; masking and etching the gate conductor; and implanting source and drain regions. The transistors formed have semiconductor strips extending from a source region to a drain region, the semiconductor strips within trenches, the trench walls insulated with a dielectric, a gate oxide formed on both vertical walls of the semiconductor strip; and gate material between the dielectric and gate oxide.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: June 13, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Yuanliang Liu, Hui Zang
  • Patent number: 11678578
    Abstract: Micro-scale thermoelectric devices having high thermal resistance and efficiency for use in cooling and energy harvesting applications and relating fabricating methods are disclosed. The thermoelectric devices include first substrates substantially parallel with second substrates. Scaffold members are deposited between the first and second substrate. The scaffold members include a plurality of cavities having sidewalls. The scaffold members may be formed from the second substrate. The sidewalls are substantially vertical with respect to the second substrate. The sidewalls may be substantially parallel. Thermoelectric materials are deposited on the sidewalls.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: June 13, 2023
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Khalil Najafi, Yi Yuan, Ethem Aktakka
  • Patent number: 11670637
    Abstract: An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: June 6, 2023
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Paul B. Fischer, Walid M. Hafez
  • Patent number: 11670664
    Abstract: The present technology relates to a light-receiving element and a distance measurement module. A light-receiving element includes: a first voltage application unit to which a voltage is applied; a first charge detection unit that is disposed at a periphery of the first voltage application unit; a second voltage application unit to which a voltage is applied; a second charge detection unit that is disposed at a periphery of the second voltage application unit; a third voltage application unit to which a first voltage is applied; and a voltage control unit that applies a second voltage to one of the first voltage application unit and the second a voltage application unit and causes the other to be in a floating state, the second voltage being different from the first voltage. The present technology is applicable to a light-receiving element.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: June 6, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Takuya Maruyama, Yuji Isogai, Tsutomu Imoto, Takuro Murase, Ryota Watanabe
  • Patent number: 11670625
    Abstract: Provided is a solid-state imaging unit that includes a stacked structure including a sensor substrate and a circuit board. The sensor board has an effective pixel region where an imaging device is disposed. The imaging device includes a plurality of pixels and is configured to receive external light in each of the pixels to generate a pixel signal. The circuit board includes a chip including a first portion and a second portion that are integrated with each other. The first portion includes a signal processing circuit that performs signal processing of the pixel signal. The second portion is disposed at a position different from a position of the first portion in an in-plane direction. Here, both the first portion and the second portion are disposed to overlap the effective pixel region in a stacking direction of the sensor board and the circuit board.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: June 6, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Masahiko Yukawa
  • Patent number: 11658197
    Abstract: A photoelectric conversion apparatus includes a first and a second multilayer wiring layer. The first or the second multilayer wiring layer is provided with a first electrode supplied with a first voltage from an outside of the photoelectric conversion apparatus. The first electrode is not connected with a second semiconductor layer.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 23, 2023
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Junji Iwata