Patents Examined by Scott B. Geyer
  • Patent number: 10483414
    Abstract: A stack-type image sensor may include a photodiode and a meta-filter. The photodiode may include a first photodiode configured to absorb first light of a first wavelength band and a second photodiode disposed on the first photodiode and configured to absorb second light of a second wavelength band. The meta-filter may include a first meta-filter disposed in a lower portion of the first photodiode and configured to reflect the first light of the first wavelength band to the first photodiode.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: November 19, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seunghoon Han, Lilong Shi, Kwanghee Lee, Changgyun Shin
  • Patent number: 10475714
    Abstract: LED system comprising a sealed internal volume containing one or more elements sensitive to the presence of Volatile Organic Compounds (VOCs), wherein in said internal volume is present a getter composition for VOCs removal comprising a combination of at least two different types of zeolite.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: November 12, 2019
    Assignee: SAES GETTERS S.p.A.
    Inventors: Alessio Corazza, Calogero Sciascia, Paolo Vacca
  • Patent number: 10468594
    Abstract: A variable resistance memory device includes a pattern of one or more first conductive lines, a pattern of one or more second conductive lines, and a memory structure between the first and second conductive lines. The pattern of first conductive lines extends in a first direction on a substrate, and the first conductive lines extend in a second direction crossing the first direction. The pattern of second conductive lines extends in the second direction on the first conductive lines, and the second conductive lines extend in the first direction. The memory structure vertically overlaps a first conductive line and a second conductive line. The memory structure includes an electrode structure, an insulation pattern on a central upper surface of the electrode structure, and a variable resistance pattern on an edge upper surface of the electrode structure. The variable resistance pattern at least partially covers a sidewall of the insulation pattern.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: November 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Woo Lee, Soon-Oh Park, Jeong-Hee Park, Hideki Horii
  • Patent number: 10468472
    Abstract: In a micro-device integration process, a donor substrate is provided on which to conduct the initial manufacturing and pixelation steps to define the micro devices, including functional, e.g. light emitting layers, sandwiched between top and bottom conductive layers. The micro-devices are then transferred to a system substrate for finalizing and electronic control integration. The transfer may be facilitated by various means, including providing a continuous light emitting functional layer, breakable anchors on the donor substrates, temporary intermediate substrates enabling a thermal transfer technique, or temporary intermediate substrates with a breakable substrate bonding layer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: November 5, 2019
    Assignee: VUEREAL INC.
    Inventors: Gholamreza Chaji, Ehsanollah Fathi
  • Patent number: 10461224
    Abstract: A molded nanoparticle phosphor for light emitting applications is fabricated by converting a suspension of nanoparticles in a matrix material precursor into a molded nanoparticle phosphor. The matrix material can be any material in which the nanoparticles are dispersible and which is moldable. The molded nanoparticle phosphor can be formed from the matrix material precursor/nanoparticle suspension using any molding technique, such as polymerization molding, contact molding, extrusion molding, injection molding, for example. Once molded, the molded nanoparticle phosphor can be coated with a gas barrier material, for example, a polymer, metal oxide, metal nitride or a glass. The barrier-coated molded nanoparticle phosphor can be utilized in a light-emitting device, such as an LED. For example, the phosphor can be incorporated into the packaging of a standard solid state LED and used to down-convert a portion of the emission of the solid state LED emitter.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: October 29, 2019
    Assignee: Nanoco Technologies Ltd.
    Inventors: Imad Naasani, Hao Pang
  • Patent number: 10446716
    Abstract: A display device includes a substrate, a first electrode, a second electrode, and a protective layer. The first electrode is disposed on the substrate. The second electrode has a first segment and a second segment. The first segment is located at a first side of the first electrode. The second segment is located at a second side of the first electrode. The second side is opposite to the first side. The protective layer overlaps the first segment and the second segment. The first segment has a length which is shorter than that of the second segment. The display device further includes a light-emitting element disposed on the substrate.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: October 15, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Chun-Hsien Lin, Jian-Jung Shih, Tsau-Hua Hsieh
  • Patent number: 10446516
    Abstract: A semiconductor package structure is disclosed. The semiconductor package structure comprises a plurality of layered structures, a plurality of wires, and a first ring structure. The wires are connected to each of the layered structures. The first ring structure is coupled to at least one of the layered structures and positioned between the wires.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: October 15, 2019
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Ping-Yuan Deng, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10446471
    Abstract: A semiconductor package includes a package substrate including a fastening section at one end and a connecting terminal section at an opposite end, at least one semiconductor device mounted on the package substrate, at least one heat pipe on the at least one semiconductor device, and a lid on the at least one semiconductor device and the at least one heat pipe. At least one end of the heat pipe is between the at least one semiconductor device and either the fastening section or the connecting terminal section.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: JaeHong Park, Hanhong Lee, Sungwoo Joo, Woon-young Baek
  • Patent number: 10431462
    Abstract: A method for forming a junction in a germanium (Ge) layer of a substrate includes arranging the substrate in a processing chamber. The method includes performing a plasma pretreatment on the substrate in the processing chamber for a predetermined pretreatment period using a pretreatment plasma gas mixture including hydrogen gas species. The method includes supplying a doping plasma gas mixture to the processing chamber including a phosphorous (P) gas species and an antimony (Sb) gas species. The method includes striking plasma in the processing chamber for a predetermined doping period. The method includes annealing the substrate during a predetermined annealing period to form the junction in the germanium (Ge) layer.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: October 1, 2019
    Assignee: Lam Research Corporation
    Inventors: Yunsang Kim, Hyuk-Jun Kwon
  • Patent number: 10431389
    Abstract: A capacitor element for use in high voltage environments is provided. More particularly, the capacitor element contains an anode that includes a solid electrolyte that overlies an anode. The anode includes a sintered porous pellet and a dielectric layer having a reduced degree of crystallinity formed on a surface of the pellet and within its pores.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 1, 2019
    Assignee: AVX Corporation
    Inventors: Jan Petrzilek, Jiri Navratil
  • Patent number: 10431525
    Abstract: Implementations of semiconductor devices may include: a first layer with a plurality of cells, each cell having a drain finger, a source finger and a gate ring; a second layer having a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad; wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer; and wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: October 1, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Woochul Jeon, Chun-Li Liu
  • Patent number: 10424670
    Abstract: A display panel with reduced power consumption is described. An example of the display panel includes an array of light emitting elements that are controllable to form an image, and a Thin-Film-Transistor (TFT) backplane comprising circuitry to drive the array of light emitting elements. The TFT backplane includes a plurality of field effect transistors (FETs). Each FET includes a source electrode, a drain electrode, a channel layer contacting the source electrode and the drain electrode, and a gate electrode adjacent to the channel layer and separated from the channel layer by an insulator. The channel layer includes a layer of metal phosphide.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Dong Yeung Kwak, Ramon C. Cancel Olmo
  • Patent number: 10424733
    Abstract: An interconnect structure for on-chip information transfer, and a method for on-chip information transfer. The interconnect structure comprises a source configured for electrically generating plasmons; a detector configured for electrically detecting the generated plasmons; and a plasmonic waveguide coupled between the source and the detector.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: September 24, 2019
    Assignee: NATIONAL UNIVERSITY OF SINGAPORE
    Inventors: Wei Du, Tao Wang, Christian Albertus Nijhuis
  • Patent number: 10403737
    Abstract: A method of forming a gate structure of a semiconductor device including depositing a high-k dielectric layer over a substrate is provided. A dummy metal layer is formed over the high-k dielectric layer. The dummy metal layer includes fluorine. A high temperature process is performed to drive the fluorine from the dummy metal layer into the high-k dielectric layer thereby forming a passivated high-k dielectric layer. Thereafter, the dummy metal layer is removed. At least one work function layer over the passivated high-k dielectric layer is formed. A fill metal layer is formed over the at least one work function layer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: September 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Che Chiang, Ju-Yuan Tzeng, Chun-Sheng Liang, Shu-Hui Wang, Kuo-Hua Pan
  • Patent number: 10392247
    Abstract: A method for fabricating a symmetrical MEMS accelerometer. For each half, etch multiple holes on the bottom of an SOI wafer; form multiple hollowed parts on the top of a silicon wafer; form silicon dioxide on the top and bottom of the silicon wafer; bond the top of the silicon wafer with the bottom of the SOI wafer; deposit silicon nitride on the bottom of the silicon wafer, remove parts of the silicon nitride and silicon dioxide to expose the bottom of the silicon wafer; etch the exposed bottom of the silicon wafer; reduce the thickness of the SOI wafer; remove the silicon nitride and exposed bottom. Bond the two halves along their bottom surface to form the accelerometer. Form a bottom cap including electrodes. Bond the bottom cap and the accelerometer. Deposit metal on top of the silicon wafer.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: August 27, 2019
    Assignee: CHINESE ACADEMY OF SCIENCES INSTITUTE OF GEOLOGY AND GEOPHYSICS
    Inventors: Lianzhong Yu, Chen Sun, Leiyang Yi
  • Patent number: 10396192
    Abstract: A method for manufacturing a HEMT transistor comprising the steps of: providing a wafer comprising a semiconductor body including a heterojunction structure formed by semiconductor materials that include elements of Groups III-V of the Periodic Table, and a dielectric layer on the semiconductor body; etching selective portions of the wafer, thus exposing a portion of the heterojunction structure; forming an interface layer by a surface reconstruction process, of a semiconductor compound formed by elements of Groups III-V of the Periodic Table, in the exposed portion of the heterojunction structure; and forming a gate electrode, including a gate dielectric and a gate conductive region, on said interface layer.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 27, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Ferdinando Iucolano, Andrea Severino, Maria Concetta Nicotra, Alfonso Patti
  • Patent number: 10384932
    Abstract: A method for manufacturing a micromechanical component, including: providing a MEMS wafer and a cap wafer; forming micromechanical structures in the MEMS wafer for at least two sensors; hermetically sealing the MEMS wafer with the cap wafer; forming a first access hole in a first cavity of a first sensor; introducing a defined first pressure into the cavity of the first sensor via the first access hole; closing the first access hole; forming a second access hole in a second cavity of a second sensor; introducing a defined second pressure into the cavity of the second sensor via the second access hole; and closing the second access hole.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: August 20, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Achim Breitling, Jan-Peter Stadler, Jochen Reinmuth, Johannes Classen
  • Patent number: 10388622
    Abstract: In some embodiments, the present disclosure relates to a method of integrated chip bonding. The method is performed by forming a metal layer on a substrate, and forming a solder layer on the metal layer. The solder layer is reflowed. The metal layer and the solder layer have sidewalls defining a recess that is at least partially filled by the solder layer during reflowing of the solder layer.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 20, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Horng Chang, Tin-Hao Kuo, Chen-Shien Chen, Yen-Liang Lin
  • Patent number: 10388637
    Abstract: A semiconductor device has a first substrate. A first semiconductor component and second semiconductor component are disposed on the first substrate. In some embodiments, a recess is formed in the first substrate, and the first semiconductor component is disposed on the recess of the first substrate. A second substrate has an opening formed through the second substrate. A third semiconductor component is disposed on the second substrate. The second substrate is disposed over the first substrate and second semiconductor component. The first semiconductor component extends through the opening. An encapsulant is deposited over the first substrate and second substrate.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 20, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: OhHan Kim, DeokKyung Yang, HunTeak Lee, InSang Yoon, Il Kwon Shim
  • Patent number: 10374136
    Abstract: A light emitting apparatus includes a positive lead terminal and a negative lead terminal, each of which includes a first main surface, a second main surface, and an end surface including a first recessed surface area extending from a first point of the first main surface in cross section, and a second recessed surface area extending from a second point of the second main surface in cross section. A distance between a first part of the end surface of the positive lead terminal and a second part of the end surface of the negative lead terminal than a first distance between the first points of the positive lead terminal and the negative lead terminal and a second distance between the second points of the positive lead terminal and the negative lead terminal. The first part and the second part are separated from the first point and the second point.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 6, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Ryohei Yamashita, Ryoichi Yoshimoto