Patents Examined by Scott J. Hawranek
  • Patent number: 6391690
    Abstract: In order to fabricate a high performance thin film semiconductor device using a temperature process in which it is possible to use inexpensive glass substrates, a highly crystalline mixed-crystallinity semiconductor film is deposited by means of PECVD using a silane as the source gas and argon as the dilution gas, then the crystallinity of this film is improved by such means as laser irradiation. Thin film semiconductor devices fabricated in this way are used in the manufacture of such things as liquid crystal displays and electronic devices. In applying the present invention to the fabrication of an active matrix liquid crystal display, it is possible to both easily and reliably fabricate a large, high-quality liquid crystal display. Additionally, in applying the present invention to the fabrication of other electronic circuits as well, it is possible to both easily and reliably fabricate high-quality electronic circuits.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: May 21, 2002
    Assignee: Seiko Epson Corporation
    Inventor: Mitsutoshi Miyasaka
  • Patent number: 6376289
    Abstract: The invention relates to a method of manufacturing a high-voltage element, in particular, but not exclusively an LDMOS transistor in SOI with a drift region (13) which has a linearly increasing doping concentration between a back-gate region (8) and a drain (6). A doping mask (15) is used for doping the drift region, in which mask the pitch between the windows becomes smaller in the direction from source to drain at least within part of the drift region. This is achieved in an embodiment by means of windows which have identical dimensions but which lie closer together in proportion as they lie closer to the domain. It was found in experiments that a smooth doping profile can be obtained in this manner, so that peaks in the doping, and thus in the electric field, are avoided. The degree of impact ionization is reduced thereby, which benefits the robustness of the transistor.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: April 23, 2002
    Assignee: U.S. Philips Corporation
    Inventor: Rene P. Zingg
  • Patent number: 6372566
    Abstract: An embodiment of the instant invention is a method of making a transistor having a silicided gate structure insulatively disposed over a semiconductor substrate, the method comprising the steps of: forming a conductive structure insulatively disposed over the semiconductor substrate (step 302 of FIG. 3); introducing a silicide enhancing substance into the conductive structure (step 304 of FIG. 3); amorphizing a portion of the conductive structure; forming a metal layer on the conductive structure (step 310 of FIG. 3); and wherein the metal layer interacts with the silicide enhancing substance in the amorphized portion of the conductive structure so as to form a lower resistivity silicide on the conductive structure. The conductive structure is, preferably, comprised of: doped polysilicon, undoped polysilicon, epitaxial silicon, or any combination thereof. Preferably, the silicide enhancing substance is comprised of: molybdenum, Co, W, Ta, Nb, Ru, Cr, any refractory metal, and any combination thereof.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: April 16, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Jorge A. Kittl, Qi-Zhong Hong
  • Patent number: 6372608
    Abstract: A method for transferring a thin film device on a substrate onto a transfer member, includes a step for forming a separation layer on the substrate, a step for forming a transferred layer including the thin film device on the separation layer, a step for adhering the transferred layer including the thin film device to the transfer member with an adhesive layer therebetween, a step for irradiating the separation layer with light so as to form internal and/or interfacial exfoliation of the separation layer, and a step for detaching the substrate from the separation layer.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: April 16, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Tatsuya Shimoda, Satoshi Inoue, Wakao Miyazawa
  • Patent number: 6358819
    Abstract: An improved dual gate oxide process for dual-gated devices using oxygen ion implantation to vary the thickness of gate oxide layers. The desired layers are identified by photoresist layer patterning prior to an ion implantation. A subsequent heat treatment oxidizes the implanted region.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: March 19, 2002
    Assignee: LSI Logic Corporation
    Inventors: Gail D. Shelton, Gayle W. Miller
  • Patent number: 6342421
    Abstract: A method of manufacturing a semiconductor device including the steps of forming an insulating film on a silicon region of a substrate having the silicon region on a surface the insulating film having an opening for forming an exposed region of the silicon region, supplying a gas containing a halogen onto the silicon region, and supplying a source gas of silicon onto the silicon region, thereby selectively depositing the silicon on the exposed region of the silicon region.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: January 29, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichiro Mitani, Ichiro Mizushima, Shigeru Kambayashi, Hirotaka Nishino, Masahiro Kashiwagi
  • Patent number: 6316324
    Abstract: A method of manufacturing a semiconductor device includes the step of doping an N-type impurity via a selective region formed on a semiconductor substrate by lithography, the step of doping a P-type impurity in the semiconductor substrate subsequent to the doping step without forming a selective region by lithography, and the step of self-aligningly forming an N-diffusion layer and a P-diffusion layer by performing wet oxidation with respect to the semiconductor substrate in which the N-type impurity and the P-type impurity are doped.
    Type: Grant
    Filed: November 5, 1996
    Date of Patent: November 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsu Honna, Yasuhiro Dohi, Yasuko Anai, Takashi Kyuho, Kazuhiro Sato
  • Patent number: 6303457
    Abstract: The present invention is a decoupling capacitor for an integrated circuit. The integrated circuit has a final metal layer which includes a power bus. The decoupling capacitor comprises a dielectric film disposed over the final metal layer and a conductive film disposed over the dielectric layer, whereby capacitance may be provided in the dielectric layer.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: October 16, 2001
    Inventors: Todd Alan Christensen, John Edward Sheet, II
  • Patent number: 6303472
    Abstract: A process for cutting a trench in a silicon monocrystal in areas defined by a mask comprises forming a mask that defines an etched area on the surface of a monocrystalline silicon wafer which is eventually covered by a thin layer of oxide. Next, ions are implanted with a kinetic energy and in a dose sufficient to amorphize the silicon down to a predefined depth within the defined area, while maintaining the temperature of the wafer sufficiently low to prevent relaxation of point defects produced in the silicon and to prevent diffusion of the implanted ions in the crystal lattice of the silicon adjacent to the amorphized region. Dislodgment and expulsion of the amorphized portion in correspondence with interface with the adjacent crystal lattice of the silicon is initiated by heating the implanted wafer.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: October 16, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giuseppe Queirolo, Giampiero Ottaviani, Gianfranco Cerofolini
  • Patent number: 6287927
    Abstract: In one aspect, the invention includes a method of thermal processing comprising: a) providing a semiconductor substrate, the semiconductor substrate supporting a material that is to be thermally processed; b) forming a sacrificial mass over the material, the mass comprising an inner portion and an outer portion, the inner portion having a different composition than the outer portion and being nearer the material than the outer portion; c) exposing the mass to radiation to heat the mass, the exposing being for a period of time sufficient for the material to absorb heat from the mass and be thermally processed thereby; and d) removing the mass from over the material.
    Type: Grant
    Filed: January 20, 2000
    Date of Patent: September 11, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Robert Burke, Mark Eyolfson
  • Patent number: 6274938
    Abstract: A resin-sealed LOC type semiconductor device includes semiconductor chip having a circuit surface on which electrodes are formed. Leads are arranged with their distal ends overlapping the semiconductor chip, electrically connected to the respective electrodes. A lead fixing resin layer is interposed between the semiconductor chip and the leads to fix them. A sealing resin layer coats the semiconductor chip and the lead to over them. The diameter of filler contained in the lead fixing resin layer is about {fraction (1/10)} to ⅕ the diameter of filler contained in the sealing resin layer, and is about {fraction (1/10)} the width of a gap between each lead and the semi conductor chip.
    Type: Grant
    Filed: September 9, 1998
    Date of Patent: August 14, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Shinji Ohuchi, Noritaka Anzai
  • Patent number: 6265236
    Abstract: A method for manufacturing a light emitting diode with the following process steps. Preparation of a substrate; production on the substrate of a series of layers which include the pn junction, that generates the radiation; production of contact layers on the surface of the layers including the pn junction and generating the radiation, and on the rear side of the substrate; and tempering of the contact layers. The method is characterized by the surface of the layers including the pn junction and generating the radiation being frosted or roughened before the contact layers are deposited. Through frosting the front side, it is possible to increase the luminous efficiency of the diodes by about 25%. Since the frost-etching process is performed before the contact layers are produced, this method can be used when aluminum is to be used as the contact material.
    Type: Grant
    Filed: July 18, 1996
    Date of Patent: July 24, 2001
    Assignee: Temic Telefunken microelectronic GmbH
    Inventor: Jochen Gerner
  • Patent number: 6265240
    Abstract: A method and apparatus for passively aligning an optical element on an optical die wherein multiple potential mounting pads are supplied for potential mounting of the optical component. Appropriate tables are generated for 1) the response of the optical detecting component for a given light power level as a function of the mounting position of the optical detecting component, and 2) the asymmetry of the light generating component. Given the two tables an algorithm is prepared for automatically determining the appropriate mounting position to provide desired detection device response characteristics for any given light generating component to be mounted on the die.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: July 24, 2001
    Assignee: Lucent Technologies, Inc.
    Inventors: Mindaugas F. Dautartas, James F. Dormer, John W. Osenbach, Edward A. Pitman
  • Patent number: 6245630
    Abstract: A spherical shaped semiconductor integrated circuit (“ball”) and a system and method for manufacturing same. The ball replaces the function of the flat, conventional chip. The physical dimensions of the ball allow it to adapt to many different manufacturing processes which otherwise could not be used. Furthermore, the assembly and mounting of the ball may facilitates efficient use of the semiconductor as well as circuit board space.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: June 12, 2001
    Assignee: Ball Semiconductor, Inc.
    Inventor: Akira Ishikawa
  • Patent number: 6245644
    Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: June 12, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Viju K. Mathews
  • Patent number: 6232207
    Abstract: In doping process for producing homojunctions in a semiconductor substrate, and the semiconductor substrate, dopants penetrate by way of diffusion employing an ultraviolet light source. A mask is introduced between the light source and the semiconductor which has regions of varying thickness. Dopant material is placed between the mask and the substrate, and the mask is then irradiated by the light source.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: May 15, 2001
    Assignee: Fraunhofer Gesellschaft zur Förderung der angewandten Forschung e.V.
    Inventor: Roland Schindler
  • Patent number: 6218260
    Abstract: Methods of forming integrated circuit capacitors include the steps of forming a lower electrode of a capacitor by forming a conductive layer pattern (e.g., silicon layer) on a semiconductor substrate and then forming a hemispherical grain (HSG) silicon surface layer of first conductivity type on the conductive layer pattern. The inclusion of a HSG silicon surface layer on an outer surface of the conductive layer pattern increases the effective surface area of the lower electrode for a given lateral dimension. The HSG silicon surface layer is also preferably sufficiently doped with first conductivity type dopants (e.g., N-type) to minimize the size of any depletion layer which may be formed in the lower electrode when the capacitor is reverse biased and thereby improve the capacitor's characteristic Cmin/Cmax ratio. A diffusion barrier layer (e.g., silicon nitride) is also formed on the lower electrode and then a dielectric layer is formed on the diffusion barrier layer.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: April 17, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Hwan Lee, Sang-Hyeop Lee, Young-Sun Kim, Se-Jin Shim, You-Chan Jin, Ju-Tae Moon, Jin-Seok Choi, Young-Min Kim, Kyung-Hoon Kim, Kab-Jin Nam, Young-Wook Park, Seok-Jun Won, Young-Dae Kim
  • Patent number: 6210980
    Abstract: An inspection pattern for a semiconductor device includes at least one inspection pattern groove and a dummy interconnection. The inspection pattern groove is formed in an interlevel insulating film or lower interconnection covering a surface of a semiconductor substrate. The dummy interconnection is formed to intersect the inspection pattern groove by burying a metal material in the inspection pattern groove. The dummy interconnection has a side wall which is exposed in the groove-like opening portion and which is inspected whether a void is present therein. An inspection method for a semiconductor device is also disclosed.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: April 3, 2001
    Assignee: NEC Corporation
    Inventor: Hiroo Matsuda
  • Patent number: 6200890
    Abstract: A fabrication method for a copper (Cu) damascene, involving etching a part of a dielectric layer after formation of the Cu conducting wires, so that the Cu conducting wires project out from the surface of the dielectric layer. A top barrier layer is formed to prevent Cu electromigration (EM) and current leakage.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: March 13, 2001
    Assignee: United Microelectronics Corp.
    Inventor: Terry Chung-Yi Chen
  • Patent number: 6180512
    Abstract: A simplified method is disclosed for forming dual damascene patterns using a phase-shifting mask in conjunction with a single photoresist process. First, a method is descried for fabricating a phase-shifting metal mask formed on a quartz substrate having opaque, transparent and semi-light-transmitting regions. The transparent regions comprise hole pattern while the semi-transmitting regions comprise line pattern for a dual damascene pattern. Then it is shown how the phase-shifting mask is used to form a dual damascene structure by forming a single photoresist on a silicon substrate having a tri-layer insulating layer, forming the hole and line patterns on the photoresist simultaneously by exposing it through the phase-shifting mask, and then transferring the patterns successively into the top and bottom layers of the insulating layer by etching. Having thus formed the vertical hole interconnect and line trench into the insulating layer, metal is deposited into the dual damascene structure.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: January 30, 2001
    Assignee: Industrial Technology Research Institute
    Inventor: Chang-Ming Dai