Abstract: The present invention relates to a process of forming a semiconductor device including forming a gallium and nitrogen bearing layer and forming at least one gate electrode over the gallium and nitrogen bearing barrier layer. The invention also includes a semiconductor device formed according to this process. In another embodiment, the invention includes a semiconductor device including a substrate, a gallium and nitrogen containing barrier layer disposed over the substrate, and at least one gate electrode disposed over the gallium and nitrogen bearing barrier layer.

Abstract: An X-ray imaging array is described together with a method for its manufacture. The array is defined by a set of PN junctions in a silicon wafer that extend all the way through between the two surfaces of the wafer. The PN junctions are formed using neutron transmutation doping that is applied to P-type silicon through a mask, resulting in an array of N-type regions (that act as pixels) in a sea of P-type material. Through suitable placement of the biassing electrodes, a space charge region is formed that is narrower at the top surface, where X-rays enter the device, and wider at the lower surface. This ensures that most of the secondary electrons, generated by the X-ray as it passes through the wafer, get collected at the lower surface where they are passed to a charge readout circuit.

Abstract: A method of manufacturing a semiconductor device can suppress an etching damage to a bipolar transistor part and a CMOS transistor part while simplifying a manufacturing process. According to this manufacturing method, an external base leader electrode layer which will form an external base leader electrode is used as an etching protection film for forming a CMOS transistor, and a layered film including a polycrystalline silicon film which will ultimately form a gate electrode is used as an etching protection film during formation of a bipolar transistor. Thereby, a step of forming the etching protection film can be utilized also as a step of forming the external base electrode and the gate electrode. Consequently, the etching damages to the bipolar transistor part and the CMOS transistor part are suppressed while simplifying the manufacturing process.

Abstract: A solid-state imaging device provided here comprises a p-type semiconductor substrate, a p-type impurity layer formed thereon, a light-intercepting part formed inside said impurity layer for storing signal charges produced through incident light, and a n-type drain part formed in a region of the substrate excluding the light-intercepting part for discharging excess charges of the light-intercepting part. As a result, sensitivity characteristics on the long wavelength side can be improved, and miniaturization can be facilitated. An n-type buried drain part for discharging charges is formed under a transfer part via a p-type impurity layer. The readout side between the light-intercepting part and the transfer part is separated by a p-type readout control part which is installed to control threshold voltage (Vt), and the non-readout side is separated by a channel stopper.

Abstract: In a method of manufacturing a semiconductor device, a gate wiring and a source wiring of a thin film transistor in the course of manufacture are connected, and are finally divided, so that it is possible to prevent breakage of a gate insulating film due to influence of plasma at the formation of various insulating films or conductive films. Specifically, openings are formed at every formation of interlayer insulating films to first layer wirings to be finally divided, and dummy electrodes not serving as electrodes are formed in the openings. When patterning a final electrode, openings are further formed in the dummy electrodes, and the first layer wirings are divided through the openings.

Abstract: A semiconductor device is formed which includes a shallow PMOS active region containing a heavy atom p-type dopant material. In an exemplary process for making a PMOS device or portion of a device, at least one PMOS gate electrode is formed over a PMOS device region of a substrate. A PMOS spacer is formed on a sidewall of a PMOS gate electrode. An amorphizing dopant material is selectively implanted into a PMOS active region using the PMOS spacer as a mask. A heavy atom p-type dopant material is selectively implanted into the PMOS active region using the PMOS spacer as a mask. The order of implantation of the amorphizing dopant material and the heavy atom p-type dopant material may be reversed.

Abstract: A method for manufacturing a liquid crystal display is provided.

Abstract: An integrated semiconductor logic gate apparatus having optimized asymmetric channel regions and method for fabricating the apparatus is disclosed. The fabrication process includes ion-implanting the drain side of the channel to produce asymmetric channels on the gate transistors by using a criss-cross form of ion implantation. The criss-cross ion-implantation is performed after formation of the multiple gate stacks and is facilitated by a patterned photoresist mask that leaves an open, unprotected region above adjacent gate stacks through which the ion-implantation is performed. The criss-cross ion-implantation includes two tilt angles that are determined by tangent expressions that factor the height of the photoresist mask, the width of the unprotected opening over pairs of gate stacks and the width of the channel regions, including a distance relating to the point where the source/drain potential barrier is a minimum beneath the overlying gate stack.

Abstract: A method for fabricating a stack capacitor with a hemi-spherical grain (HSG) structure is provided. A dielectric layer with a cave is first formed on a substrate. A conformal multi-layer amorphous silicon layer with low dopant concentration is formed over the substrate to cover the cave surface. An amorphous silicon layer with a sufficiently high dopant concentration is formed on the multi-layer amorphous silicon layer to fill the cave. After a planarization process, a remaining portion of the multi-layer amorphous silicon layer and the amorphous silicon layer form a storage node to fill the cave. The dielectric layer is removed to expose the storage node. A HSG is formed on the exposed surface of the storage node. An annealing process is performed to obtain a uniform dopant concentration. A dielectric thin film is formed over the storage node and the HSG layer. An upper electrode is formed to accomplish the stack capacitor.

Abstract: A method of fabricating a metal gate includes forming a gate insulating layer on a provided substrate, forming a PVD titanium nitride layer on the gate insulating layer, forming a CVD titanium nitride layer on the PVD titanium nitride layer, and forming a CVD tungsten layer on the CVD titanium nitride layer. The CVD tungsten layer, the CVD titanium nitride layer, and the PVD titanium nitride layer are later patterned to form the metal gate.

Abstract: Low resistivity metal silicide layers are formed on a gate electrode and source/drain regions at an optimum thickness for reducing parasitic series resistances with an attendant consumption of silicon from the gate electrode and source/drain regions. Consumed silicon from the gate electrode and source/drain regions is then replaced employing metal induced crystallization, thereby avoiding a high leakage current. Embodiments include depositing a layer of amorphous silicon on the metal silicide layers and heating at a temperature of about 400.degree. C. to about 600.degree. C. initiating metal induced crystallization, thereby causing the metal silicide layers grow upwardly as silicon in the underlying gate electrode and source/drain regions is replaced.

Abstract: A method of forming a pair of field effect transistors having different thickness gate dielectric layers includes, a) providing a first region on a substrate for formation of a first field effect transistor s having a first gate dielectric layer of a first thickness and providing a second region on the substrate for formation of a second field effect transistor having a second gate dielectric layer of a second thickness; b) providing the first gate dielectric layer and a first conductive gate layer over the first and second regions; c) patterning the first conductive layer to define a first gate of the first field effect transistor in the first region while leaving the first conductive layer not patterned for gate formation for the second field effect transistor in the second region; d) after defining the first gate, stripping the first conductive layer and the first gate dielectric layer from the second region; e) after stripping the first conductive layer and the first gate dielectric layer from the second

Abstract: A method of fabricating a CMOSFET includes the steps of selectively forming first and second conductive type wells in a semiconductor substrate, forming an isolation insulating layer at interface of the first and second conductive type wells, forming a first gate electrode formed of a first conductive type electrode over a predetermined area of the second conductive type well and a second gate electrode successively formed of a second conductive type electrode, a diffusion preventing layer, and the first conductive type electrode over a predetermined area of the first conductive type well, forming sidewall spacers on both sides of each of the first and second gate electrodes, forming second and first conductive type impurity regions under surfaces of the first and second conductive type wells, respectively, at both sides of the first and second gate electrodes and the their sidewall spacers, and forming a silicide layer on the first and second gate electrodes and on the semiconductor substrate where the first

Abstract: A gate oxide film is formed on a thin-film SOI substrate or on a single crystalline silicon substrate and a gate is formed on the gate oxide film. The surfaces of a single crystalline silicon at diffusion layer regions on opposite sides of the gate are cleaned and an amorphous silicon film is formed thereon and on the side walls of the gate. Impurity ions are implanted in the amorphous silicon film, which is then converted into recrystallized silicon films by annealing. An interlayer insulator film is formed and another annealing is conducted. As a result, impurity ions in the recrystallized silicon films diffuse into the diffusion layer region of the single crystalline silicon and are activated to form a source and a drain.

Abstract: A method of forming film transistor includes, a) forming a thin film transistor layer of semiconductive material; b) providing a gate operatively adjacent the thin film transistor layer; c) forming at least one electrically conductive sidewall spacer over at least one lateral edge of the gate, the spacer being electrically continuous therewith; and d) providing a source region, a drain region, a drain offset region, and a channel region in the thin film transistor layer; the drain offset region being positioned operatively adjacent the one electrically conductive sidewall spacer and being gated thereby. The spacer is formed by anisotropically etching a spacer forming layer.

Abstract: In a surface of a silicon substrate of one conductivity type, there are formed a plurality of depressions or recesses, gate regions of opposite conductivity type are formed at bottoms of respective recesses, gate electrodes are provided on respective gate regions, and an electrically conductive block is joined to the surface of the semiconductor substrate. Between the surface of the semiconductor substrate and the electrically conductive block a contact region having a high impurity concentration and/or an electrically conductive material layer may be provided in order to improve electrical and mechanical properties of the contact between the semiconductor substrate and the electrically conductive block. The gate region can have a high impurity concentration and a distance between a channel region and the electrically conductive block can be very small.

Abstract: A capacitor for a semiconductor memory device and a method for manufacturing the same are provided. A lower electrode of a capacitor according to the present invention has a structure in which a first conductive layer and a second conductive layer are sequentially deposited and an HSG is selectively formed on the surface thereof. The first conductive layer is composed of an amorphous or a polycrystalline silicon film having a low concentration of impurities. The second conductive layer is composed of an amorphous silicon film having a high concentration of impurities. According to the present invention, it is possible to obtain a desirable Cmin/Cmax ratio in the lower electrode of the capacitor having an HSG silicon layer and to prevent diffusion of impurities from the lower electrode of the capacitor.

Abstract: Method of fabricating thin-film transistors in which contact with connecting electrodes becomes reliable. When contact holes are formed, the bottom insulating layer is subjected to a wet etching process, thus producing undercuttings inside the contact holes. In order to remove the undercuttings, a light etching process is carried out to widen the contact holes. Thus, tapering section are obtained, and the covering of connection wiring is improved.

Abstract: Methods of forming a field oxide region and an adjacent active area region are described. A semiconductive substrate is masked with an oxidation mask while an adjacent area of the substrate remains unmasked. The substrate is exposed to conditions effective to form a field oxide region in the adjacent area. The field oxide region has a bird's beak region which extends toward the active area. A mass of material is formed over at least a portion of the bird's beak region. In a preferred implementation, the mass of material is formed from material which is different than the material from which the oxidation mask and the field oxide region are formed. According to one aspect of the invention, the material comprises polysilicon. In another preferred implementation, such different material comprises a spacer which is formed over at least a portion of the oxidation mask. Preferably, an undercut region is formed under the mass or spacer and subsequently filled with oxide material.

Abstract: Method for manufacturing TFTs including steps of forming a control electrode and control electrode line on a substrate, forming insulating film on the control electrode and the control electrode line, cleaning the substrate with the insulating film formed by a chemical or physical means, forming oxide film on the surface of the control electrode and control electrode line exposed by a film lacking portion generated in the insulating film after cleaning, forming a semiconductor layer via the insulating film on the control electrode, and forming a pair of electrodes constituting a semiconductor element together with the semiconductor layer.