Patents Examined by Scott J. Hawranek
  • Patent number: 5913113
    Abstract: A method for fabricating a thin film transistor of a liquid crystal display device comprising the steps of introducing a dopant into an indium tin oxide layer or gate insulating layer with an ion shower doping process, forming an amorphous silicon layer thereon, exposing the amorphous silicon layer with a laser beam to diffuse the dopant into the amorphous layer and activate the dopant. As a result of the laser annealing, an n or p-type ohmic polysilicon layer and an intrinsic polysilicon channel layer can be formed. A gate electrode can also be formed on a gate insulating layer using a gate mask.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: June 15, 1999
    Assignee: LG Electronics Inc.
    Inventor: Seong Moh Seo
  • Patent number: 5904519
    Abstract: A method of manufacturing a semiconductor device made up of a Bi-CMOS integrated circuit with the performance of MOS and bipolar elements enhanced. A semiconductor substrate surface is selectively oxidized to divide surface into a bipolar element forming area and a MOS element forming area. Next, the entire substrate surface is oxidized to form an oxide film 9, after which high-density ions are implanted into a collector leading area. Then, driving-in of the collector leading area is performed by performing heat treatment in an oxidizing atmosphere while forming an oxide film 9b on the collector leading area and another oxide film 9a on the MOS element forming area. Subsequently, the oxide film is etched all over the semiconductor substrate surface by the thickness of the oxide film 9a to expose the semiconductor substrate surface of the MOS element forming area. Lastly, the substrate surface is entirely oxidized to form a gate insulation film thinner than the oxide film 9.
    Type: Grant
    Filed: June 19, 1997
    Date of Patent: May 18, 1999
    Assignee: NEC Corporation
    Inventor: Masaru Wakabayashi
  • Patent number: 5903013
    Abstract: A thin film transistor includes a substrate, a gate electrode formed on the substrate, and including opposing edge portions and a middle portion. An insulating film is formed on the surface of the gate electrode having a greater thickness on one of the gate edge portions. An active region is formed on the surface of the insulating film and the exposed substrate. The active region includes an off-set region, a channel region, a source region, and a drain region.
    Type: Grant
    Filed: November 18, 1996
    Date of Patent: May 11, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Sung Kge Park
  • Patent number: 5897381
    Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: April 27, 1999
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Nicholas Eib, Jon S. Owyang
  • Patent number: 5888859
    Abstract: A method of making a semiconductor device includes forming a recess in a compound semiconductor substrate using a patterned insulating film on a surface of the substrate, implanting dopant ions at the bottom of the recess to form a channel region, and depositing a refractory metal film. The refractory metal film is etched, using a resist pattern, to form a gate electrode and additional dopant ions are implanted to form relatively highly doped regions intersecting the channel region. Very highly doped regions are formed my implantation, after removing the insulating film, using the gate electrode and remainder of the resist mask as an implantation mask. After stripping the resist, annealing to activate the implanted ions, and depositing a passivating film on the substrate and gate electrode, source and drain electrodes are formed.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: March 30, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tomoki Oku, Shinichi Miyakuni, Nobuyuki Kasai, Yasutaka Kohno, deceased
  • Patent number: 5879969
    Abstract: In a thin-film insulated gate type field effect transistor having a metal gate in which the surface of the gate electrode is subjected to anodic oxidation, a silicon nitride film is provided so as to be interposed between the gate electrode and the gate insulating film to prevent invasion of movable ions into a channel, and also to prevent the breakdown of the gate insulating film due to a potential difference between the gate electrode and the channel region. By coating a specific portion of the gate electrode with metal material such as chrome or the like for the anodic oxidation, and then removing only the metal material such as chrome or the like together with the anodic oxide of the metal material such as chrome or the like, an exposed portion of metal gate (e.g. aluminum) is formed, and an upper wiring is connected to the exposed portion.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: March 9, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hongyong Zhang, Yasuhiko Takemura
  • Patent number: 5877083
    Abstract: It is intended to reduce occurrences of interlayer short-circuiting due to pinholes existing in an interlayer insulating film particularly in a circuit formed on an insulating substrate. A wiring line mainly made of an anodizable metal such as aluminum, tantalum, titanium, or the like is formed on an insulating surface, and an interlayer insulating film is so formed as to cover the metal wiring line. The substrate is then immersed in an electrolyte of, for instance, ammonium tartrate. Portions of the metal wiring line which are exposed by the pinholes of the interlayer insulating film are selectively anodized by allowing a current to flow through the wiring line by using it as one of the electrodes and gradually increasing a voltage difference between the wiring line and the opposed electrode. Thus, insulation performance of the interlayer insulating film is improved.
    Type: Grant
    Filed: October 30, 1995
    Date of Patent: March 2, 1999
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 5861326
    Abstract: In a semiconductor integrated circuit for forming an offset gate structure by utilizing an anodic oxidation film fabricated around a gate electrode, even when a length of a gate line becomes long, the anodic oxidation film can be made uniform, and also electric characteristics of thin-film transistors can be matched with each other. In a semiconductor integrated circuit manufacturing method, a large number of insulated gate type field-effect transistors are connected with respect to a single gate line.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: January 19, 1999
    Assignee: Semiconductor Energy Laboratory Co. Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto