Patents Examined by Scott Stowe
  • Patent number: 10861745
    Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan Syun David Yang, Li-Te Lin, Chun-Jui Huang
  • Patent number: 10847531
    Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Steve Weiyi Yang, Wenguang Shi
  • Patent number: 10825935
    Abstract: A trench MOS-type Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer opposite to the first semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer opposite to the second semiconductor layer, an insulating film covering the inner surface of the trench of the second semiconductor layer, and a trench MOS gate that is embedded in the trench of the second semiconductor layer so as to be covered with the insulating film and is in contact with the anode electrode.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: November 3, 2020
    Assignees: TAMURA CORPORATION, National Institute of Information and Communications Technology
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Patent number: 10811595
    Abstract: Techniques are disclosed for forming a logic device including integrated spin-transfer torque magnetoresistive random-access memory (STT-MRAM). In accordance with some embodiments, one or more magnetic tunnel junction (MTJ) devices may be formed within a given back-end-of-line (BEOL) interconnect layer of a host logic device. A given MTJ device may be formed, in accordance with some embodiments, over an electrically conductive layer configured to serve as a pedestal layer for the MTJ's constituent magnetic and insulator layers. In accordance with some embodiments, one or more conformal spacer layers may be formed over sidewalls of a given MTJ device and attendant pedestal layer, providing protection from oxidation and corrosion. A given MTJ device may be electrically coupled with an underlying interconnect or other electrically conductive feature, for example, by another intervening electrically conductive layer configured to serve as a thin via, in accordance with some embodiments.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Kevin J. Lee, Oleg Golonzka, Tahir Ghani, Ruth A. Brain, Yih Wang
  • Patent number: 10802348
    Abstract: An array substrate, display panel and display device. The array substrate includes: a source-drain metal layer, a pixel electrode layer, an insulation layer located between the source-drain metal layer and the pixel electrode layer, and a plurality of sub-pixels distributed in an array. Each sub-pixel corresponds to a drain electrode contained in source-drain metal layer, a pixel electrode contained in pixel electrode layer, and a drain through-hole defined in insulation layer. The pixel electrode is connected to the drain electrode via the drain through-hole. For any one row of the array, in a column direction, each drain electrode through hole is located at the same side of the sub-pixel 10 corresponding to the drain electrode through hole. The sub-pixels includes two adjacent support sub-pixels in a row direction, and the two drain through-holes respectively corresponding to the two adjacent support sub-pixels are unaligned in the column direction.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: October 13, 2020
    Assignee: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Qian Yang, Huanda Wu, Lei Zhang, Xiufeng Zhou, Boping Shen, Zhaokeng Cao, Huangyao Wu
  • Patent number: 10804263
    Abstract: A power MOSFET IC device including a source-down enhancement mode transistor formed in a semiconductor substrate and a depletion mode transistor formed in a doped region of the semiconductor substrate. A gate terminal of the depletion mode transistor is formed over at least a portion of the doped region as a field plate that is switchably connectable to a source terminal of the source-down enhancement mode transistor. A control circuit may be provided to facilitate a connection between the gate terminal of the depletion mode transistor and the source terminal of the source-down enhancement mode transistor when the power MOSFET integrated circuit is in an OFF state. The control circuit may also be configured to facilitate connection of the gate terminal of the depletion mode transistor to a gate terminal of the source-down enhancement mode FET device or to an external driver that provides a reference voltage, when the power MOSFET is in an ON state.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 13, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Frank Baiocchi
  • Patent number: 10800650
    Abstract: A MEMS element within a semiconductor device is enclosed within a cavity bounded at least in part by hydrogen-permeable material. A hydrogen barrier is formed within the semiconductor device to block propagation of hydrogen into the cavity via the hydrogen-permeable material.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: October 13, 2020
    Assignee: SiTime Corporation
    Inventors: Charles I. Grosjean, Paul M. Hagelin, Michael Julian Daneman, Ginel C. Hill, Aaron Partridge
  • Patent number: 10784781
    Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chu Fu Chen, Chi-Feng Huang, Chia-Chung Chen, Chin-Lung Chen, Victor Chiang Liang, Chia-Cheng Pao
  • Patent number: 10777707
    Abstract: A group-Ill nitride stacked body includes a substrate, an n-type first AlGaN layer expressed by the composition formula AlXGa1-XN (0<X?1), and a second AlGaN layer which is disposed between the substrate and the n-type first AlGaN layer and which is expressed by the composition formula AlYGa1-YN (0.5<Y?1, where Y<X). A group-III nitride light-emitting element comprises an active layer which is disposed on the n-type first AlGaN layer of the group-Ill nitride stacked body and which includes at least one well layer. The well layer of the active layer is an AlGaN layer expressed by the composition formula AlWGa1-WN (0<W<1), where the Al composition W is such that W?Y.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: September 15, 2020
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Toshiyuki Obata
  • Patent number: 10770591
    Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Sameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
  • Patent number: 10763254
    Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: September 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Soo Kim, Gi Gwan Park, Jung Hun Choi, Koung Min Ryu, Sun Jung Lee
  • Patent number: 10753963
    Abstract: A current sensor integrated circuit includes a lead frame having a primary conductor and at least one secondary lead, a semiconductor die disposed adjacent to the primary conductor, an insulation structure disposed between the primary conductor and the semiconductor die, and a non-conductive insulative material enclosing the semiconductor die, the insulation structure, a first portion of the primary conductor, and a first portion of the at least one secondary lead to form a package. The first portion of the at least one secondary lead (between a first end proximal to the primary conductor and a second end proximal to the second, exposed portion of the at least one secondary lead) has a thickness that is less than a thickness of the second, exposed portion of the least one secondary lead. A distance between the second, exposed portion of the primary conductor and the second, exposed portion of the at least one secondary lead is at least 7.2 mm.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 25, 2020
    Assignee: Allegro MicroSystems, LLC
    Inventors: Shaun D. Milano, Shixi Louis Liu
  • Patent number: 10756211
    Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: August 25, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keum Seok Park, Jungho Yoo, Jinyeong Joe, Bonyoung Koo, Dongsuk Shin, Hongsik Yoon, Byeongchan Lee
  • Patent number: 10748921
    Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Liu Liu, David Daycock, Rithu K. Bhonsle, Giovanni Mazzone, Narula Bilik, Jordan D. Greenlee, Minsoo Lee, Benben Li
  • Patent number: 10741729
    Abstract: A light emitting apparatus includes an electrically insulating base member; a first electrically conductive pattern portion and a second electrically conductive pattern portion formed on an upper surface of the base member; a plurality of intermediate electrically conductive pattern portions arranged between the first and second electrically conductive pattern portions; at least one light emitting device mounted on at least one of the intermediate electrically conductive pattern portions; a protection element mounted on the first and second electrically conductive pattern portions; and a resin portion disposed around the at least one light emitting device such that (i) the first and second electrically conductive pattern portions are partially covered by the resin portion and partially exposed from the resin portion, and (ii) the protection element is covered by the resin portion.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: August 11, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Tomonori Miyoshi, Kenji Ozeki, Tomoaki Tsuruha
  • Patent number: 10741570
    Abstract: A nonvolatile memory device includes an active region extending in a first direction and including a source region and a drain region that are respectively disposed at both ends of the active region, a gate electrode pattern extending in a second direction and disposed between the source region and the drain region, wherein the second direction extends across the first direction, a gate insulation pattern disposed between the gate electrode pattern and the active region, a source contact plug and a drain contact plug respectively coupled to the source region and the drain region, and a coupling contact plug disposed over the gate electrode pattern and insulated from the gate electrode pattern.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Sung Kun Park
  • Patent number: 10737936
    Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer; wherein the plurality of scribe lines protrudes from a third surface of the second wafer, and the third surface is between the first surface and the second surface.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Cheng Shen, Yi-Hsien Chang, Yi-Heng Tsai, Chun-Ren Cheng
  • Patent number: 10734380
    Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Min Jeong, Kee-Sang Kwon, Jin-Wook Lee, Ki-Hyung Ko, Sang-Jine Park, Jae-Jik Baek, Bo-Un Yoon, Ji-Won Yun
  • Patent number: 10734411
    Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Tang Lin, Chun-Hsiung Tsai, Clement Hsingjen Wann
  • Patent number: 10724981
    Abstract: A microfluidic chip suitable for detecting a microdroplet includes a first component, a second component, a channel layer, and a semiconductor chip. The first component includes a first substrate, a first electrode layer, and a first dielectric layer, wherein the first electrode layer is located between the first substrate and the first dielectric layer. The second component is disposed opposite to the first component and includes a second substrate, a second electrode layer, and a second dielectric layer. The channel layer is located between the first component and the second component. The semiconductor chip is disposed at one side of the first substrate and is exposed to the channel layer to assist in treating or detecting a sample or microdroplet. The microdroplet in the sample entering the channel layer is reacted with the semiconductor chip, and thus the sample is detected.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: July 28, 2020
    Inventors: Shih-Kang Fan, Chih-Yuan Liang, Chia-Chann Shiue, Yuan-Sheng Lee, Yu-Kai Lai