Abstract: Method, apparatus, and computer program product embodiments of the invention are disclosed for entering an accessory docking mode.

Abstract: Universal serial bus (USB) devices may be redirected to a server to create USB virtual devices. Each of the USB devices to be redirected may have one or more partitions but each partition may not be suitable for redirection. A user may select one or more partitions for redirection. The server may read the selected partitions. The server will create virtual volumes for only the selected partitions and will mount a file system for each of the selected partitions only.

Abstract: A mechanism is provided for balancing workload to one or more storage disks in a plurality of storage disks during redistribution or replication associated with adding or removing a storage disk to the plurality of storage disks. Historical information in collected information from the plurality of storage disks is analyzed to identify I/O operation patterns on a per storage disk level. An average amount of I/O operations that occur within each storage disk for a given time period are identified. For each storage disk that is impacted, a disk on/off-hoarding plan is generated that identifies a subset of I/O operations from a set of I/O operations to execute in the given time period using the average amount of I/O operations that historically occur within the storage disk that is impacted during the given time period. The subset of I/O operations are then executed in the given time period.

Abstract: A method for hiding implicit bit corrections in a partial product adder array in a binary and hexadecimal floating-point multiplier such that no additional adder stages are needed for the implicit bit corrections. Two leading-one correction terms are generated for the fraction in the multiplier floating-point number and two leading-one correction terms are generated for the fraction in the multiplicand floating-point number. The floating-point numbers may be single-precision or double-precision. Each leading-one correction term for the single-precision case is appended to the left of an intermediate partial product sum in the adder array that is an input to an adder so as to not to extend the bits in the input further to the left than the bits in another input to the adder. Each leading-one correction term for the double-precision case replaces an adder input that is unused when base-2 floating-point numbers are multiplied.

Abstract: A hosting computer accepts specialized keyboard and mouse input via a generic device redirection channel from a client computer. A device manager has interfaces to the generic device redirection channel and to a system queue for communicating keyboard and mouse input events to an operating system. The system queue has a separate interface to a virtual channel for receiving redirected keyboard and mouse input from standard keyboard and mouse devices. The device manager identifies keyboard and mouse functions of other devices connected to the client computer and having device input redirected to the hosting computer via the generic device redirection channel, and establishes respective device context engines for handling input events from the identified functions. The device context engines open the keyboard and mouse functions, and upon receiving input events from functions, queues the input events on the system queue to communicate them to the operating system.

Abstract: Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory.

Abstract: A checkpointing method for creating a file representing a restorable state of a virtual machine in a computing system, comprising identifying processes executing within the virtual machine that may store confidential data, and marking memory pages and files that potentially contain data stored by the identified processes; or providing an application programming interface for marking memory regions and files within the virtual machine that contain confidential data stored by processes; and creating a checkpoint file, by capturing memory pages and files representing a current state of the computing system, which excludes information from all of the marked memory pages and files.

Abstract: A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit. Each of the data sources is capable of providing a data stream. The memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to route the respective data stream to the processing unit via the respective buffer. Each of the buffers has buffer characteristics which are variable and which comprise at least the amount of free memory of the respective buffer. The memory control unit is arranged to allocate and de-allocate memory regions to and from each of the buffers in dependence of the buffer characteristics of the respective buffer, thereby allowing for re-allocation of memory of the memory unit among the buffers. A method of operating a system on chip is also described.

Abstract: According to at least one example embodiment, a multi-chip system includes multiple chip devices configured to communicate to each other and share resources. According to at least one example embodiment, a method of memory allocation in the multi-chip system comprises managing, by each of one or more free-pool allocator (FPA) coprocessors in the multi-chip system, a corresponding list of pools of free-buffer pointers. Based on the one or more lists of free-buffer pointers managed by the one or more FPA coprocessors, a memory allocator (MA) hardware component allocates a free buffer, associated with a chip device of the multiple chip devices, to data associated with a work item. According to at least one aspect, the data associated with the work item represents a data packet.

Abstract: A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract: Provided herein is a compressed cache design to predict indirect branches in a microprocessor based on the characteristics of the addresses of the branch instructions. In one aspect, a method for predicting a branch target T in a microprocessor includes the following steps. A compressed count cache table (CTABLE) of branch targets indexed using a function combining a branch address and a branch history vector for each of the targets is maintained, wherein entries in the CTABLE contain only low-order bits of each of the targets in combination with an index bit(s) I. A given one of the entries is obtained related to a given one of the branch targets and it is determined from the index bits I whether A) high-order bits of the target are equal to the branch address, or B) the high-order bits of the target are contained in an auxiliary cache table (HTABLE).

Abstract: A first storage system is configured as a proxy for a logical volume stored on a second storage system in a distributed computing environment. A probe request verifying availability of the logical volume is conveyed to an identified port, and upon receiving a response from a second storage system verifying the availability of the logical volume for an I/O request, the I/O request is conveyed to the identified port, a result of the I/O request is received from the identified port, the result is conveyed to the host computer.

Abstract: A processor of an aspect includes a plurality of packed data registers. The processor also includes a unit coupled with the packed data registers. The unit is operable, in response to a limited range vector memory access instruction. The instruction is to indicate a source packed memory indices, which is to have a plurality of packed memory indices, which are to be selected from 8-bit memory indices and 16-bit memory indices. The unit is operable to access memory locations, in only a limited range of a memory, in response to the limited range vector memory access instruction. Other processors are disclosed, as are methods, systems, and instructions.

Abstract: Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second packed data operation mask having second packed data operation mask bits. Each packed data operation mask bit of first mask corresponds to a packed data operation mask bit of second mask in corresponding position. Modify first flag to first value if bitwise AND of each packed data operation mask bit of first mask with each corresponding packed data operation mask bit of second mask is zero. Otherwise modify first flag to second value. Modify second flag to third value if bitwise AND of each packed data operation mask bit of first mask with bitwise NOT of each corresponding packed data operation mask bit of second mask is zero. Otherwise modify second flag to fourth value.

Abstract: An apparatus includes multiple media processing modules and a control unit. The media processing modules are configured to exchange digital media signals over a shared bus. The control unit is configured to determine a desired connectivity scheme among the media processing modules, to adaptively define, based on the desired connectivity scheme, connections that transfer the media signals among the media processing modules over the shared bus, and to instruct the media processing modules to establish the connections, by communicating with the media processing modules over a control interface that is independent of the shared bus.

Abstract: A system and method for maintaining the safety of volume operations. A storage controller receives a request to delete a first volume. In response to this request, the storage controller can delete a link between the first volume and its anchor medium. The storage controller can also delay the deletion of the first volume's anchor medium. Later on, if the user wishes to restore the first volume, the storage controller can reconnect the first volume to its previous anchor medium, effectively restoring the first volume to its former state and undoing the deletion operation.

Abstract: A method of reading data in an electronic system includes detecting whether a trigger signal in the electronic system is enabled, the trigger signal being selectively enabled according to at least one operating condition of the electronic system, as a consequence of detecting that the trigger signal is enabled, changing a size of read-ahead data based on the enabled trigger signal, and performing a read operation based on a read command and the changed size of the read-ahead data.

Abstract: The present invention provides a status switching method applied to a slave device. The status switching method includes: receiving a command wrapper from a host device; receiving a status query command corresponding to the command wrapper from the host device; transmitting a status wrapper to the host device in response to the status query command; and refusing to enter a low-power status corresponding to a switch status request when the switch status request is received during a specific period, wherein the specific period starts when the command wrapper is received and ends when the status wrapper is transmitted.

Abstract: An interrupt controller includes a priority level arbitrator (8) including multiple stages. The stages include at least one stage comprising a plurality of interrupt selectors formed of a multiplexer (14) for selecting between a pair of potentially concurrently asserted interrupt signals in dependence upon selection data. The selection data is determined in advance by a priority level comparator (12) using priority level data associated with the respective interrupt signals.