Patents Examined by Sean D Rossiter
  • Patent number: 11507303
    Abstract: Aspects of a storage device including a memory and a controller are provided. The memory includes non-volatile memory and volatile memory. The controller may determine whether first data is available at a system-level memory location during a first programming stage of a two-stage programming sequence. The controller may read the first data from the system-level memory location when the page data is available at the system-level memory location. Alternatively, the controller may read the first data from the non-volatile memory when the page data is not available at the system-level memory location. Thus, the controller may perform a first programming operation associated with the first programming stage using the first data, thereby improving memory programming performance of the storage device.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 22, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amit Sharma, Sourabh Sankule, Dinesh Kumar Agarwal, Chetan Agrawal
  • Patent number: 11507286
    Abstract: A storage management technique involves: determining a spare degree of physical storage space of a file system and access characteristics of the file system; determining, using a provision operation classification model and based on the spare degree and the access characteristics, a target storage provision operation to be performed for the file system from multiple storage provision operations, wherein the multiple storage provision operations include at least a storage space expansion operation and a storage space reclamation operation, and the provision operation classification model characterizes an association relationship between different spare degrees and different access characteristics of the file system and the multiple storage provision operations; and performing the determined target storage provision operation for the file system. Accordingly, a better balance is achieved between storage efficiency and I/O performance.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: November 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Sicong Yao, Liang Huang, Ruipeng Yang, Jianhua Shao, Xianlong Liu
  • Patent number: 11507280
    Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of a data interface circuit of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: November 22, 2022
    Assignee: RAMBUS INC.
    Inventors: Frederick A. Ware, Robert E. Palmer, John W. Poulton
  • Patent number: 11494313
    Abstract: A storage device having improved operation speed may include a main memory configured to store first to N-th meta data, a cache memory including first to N-th dedicated areas respectively corresponding to areas in which the first to N-th meta data are stored, and a processor configured to store data accessed according to requests provided from a host among the first to N-th meta data in the first to N-th dedicated areas, respectively. A size of the first to N-th dedicated areas may be determined according to the number of times each of the first to N-th meta data is accessed by the requests.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: November 8, 2022
    Assignee: SK hynix Inc.
    Inventor: Do Hun Kim
  • Patent number: 11487438
    Abstract: Systems, methods, and computer readable storage mediums for discovering volumes which are good candidates for space reclamation. A storage subsystem identifies the file system storage capacity for a given volume from the file system metadata of the given volume. Then, the storage subsystem compares the file system capacity of the given volume to the allocated capacity on the storage subsystem. If the allocated capacity is greater than the file system capacity by a given threshold, the storage subsystem marks the given volume as a candidate for space reclamation and generates an alert to the user to reclaim the space of the given volume.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: November 1, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Frederic Lherault, Neil Vachharajani
  • Patent number: 11487666
    Abstract: A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 11481325
    Abstract: A system for managing a virtual machine is provided. The system includes a processor configured to initiate a session for accessing a virtual machine by accessing an operating system image from a system disk and monitor read and write requests generated during the session. The processor is further configured to write any requested information to at least one of a memory cache and a write back cache located separately from the system disk and read the operating system image content from at least one of the system disk and a host cache operably coupled between the system disk and the at least one processor. Upon completion of the computing session, the processor is configured to clear the memory cache, clear the write back cache, and reboot the virtual machine using the operating system image stored on the system disk or stored in the host cache.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: October 25, 2022
    Assignee: Citrix Systems, Inc.
    Inventors: Yuhua Lu, Graham MacDonald, Lanyue Xu, Roger Cruz
  • Patent number: 11474820
    Abstract: Apparatuses and methods related to commands to transfer data and/or perform logic operations are described. For example, a command that identifies a location of data and a target for transferring the data may be issued to a memory device. Or a command that identifies a location of data and one or more logic operations to be performed on that data may be issued to a memory device. A memory module may include different memory arrays (e.g., different technology types), and a command may identify data to be transferred between arrays or between controllers for the arrays. Commands may include targets for data expressed in or indicative of channels associated with the arrays, and data may be transferred between channels or between memory devices that share a channel, or both. Some commands may identify data, a target for the data, and a logic operation for the data.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Frank F. Ross, Matthew A. Prather
  • Patent number: 11474701
    Abstract: Determining effective space utilization in a storage system, including: identifying an amount of data stored within the storage system that is associated with a user-visible entity; identifying an amount of data stored within the storage system that is associated with all snapshots of the user-visible entity; and reporting, in dependence upon the an amount of data stored within the storage system that is associated with the user-visible entity and the amount of data stored within the storage system that is associated with all snapshots of the user-visible entity, a total capacity utilization associated with the user-visible entity.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: October 18, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: Matthew Fay, John Colgrove, Martin Harriman
  • Patent number: 11455248
    Abstract: A semiconductor device performs a software lock-step. The semiconductor device includes a first circuit group including a first Intellectual Property (IP) to be operated in a first address space, a first bus, and a first memory, a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory, a third bus connectable to a third memory, and a transfer control circuit coupled to the first to third buses. when the software lock-step is performed, the second circuit group converts an access address from the second IP to the second memory such that an address assigned to the second memory in the second address space is a same as an address assigned to the first memory in the first address space.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: September 27, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Nakamura, Akihiro Yamamoto, Kazuaki Terashima, Manabu Koike
  • Patent number: 11449231
    Abstract: Methods and systems are provided for modifying configuration of a storage system using artificial intelligence. An exemplary method comprises collecting, over a period of time, health and parameter information of the storage system. The method comprises predicting, using a machine learning algorithm, upcoming events that may degrade performance of the storage system based on the health and parameter information. The method comprises determining that the storage system will not operate in accordance with a set of goals based on the upcoming events. In response to determining that the storage system will not operate in accordance with the set of goals, the method comprises generating parameter changes, and applying the parameter changes to the storage system.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: September 20, 2022
    Assignee: Acronis International GmbH
    Inventors: Serguei Beloussov, Oleg Melnikov, Kirill Korotaev, Sergey Ulasen
  • Patent number: 11435920
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: September 6, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Karin Inbar
  • Patent number: 11436038
    Abstract: Hypervisor-independent block-level live browse is used for directly accessing backed up virtual machine (VM) data. Hypervisor-free file-level recovery (block-level pseudo-mount) from backed up VMs also is disclosed. Backed up virtual machine (“VM”) data can be browsed without needing or using a hypervisor. Individual backed up VM files can be requested and restored to anywhere without a hypervisor and without the need to restore the rest of the backed up virtual disk. Hypervisor-agnostic VM backups can be browsed and recovered without a hypervisor and from anywhere, and individual backed up VM files can be restored to anywhere, e.g., to a different VM platform, to a non-VM environment, without restoring an entire virtual disk, and without a recovery data agent at the destination.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: September 6, 2022
    Assignee: Commvault Systems, Inc.
    Inventors: Henry Wallace Dornemann, Rahul S. Pawar, Amit Mitkar, Sunil Kumar Gutta, Sumedh Pramod Degaonkar, Jianwei Chen
  • Patent number: 11429528
    Abstract: Methods, systems, and devices for a split cache for address mapping data are described. A memory system may include a cache (e.g., including a first and second portion) for storing data that indicates a mapping between logical addresses associated with a host system and physical addresses of the memory system. The memory system may store data (e.g., the address mapping data) within the first portion of the cache. Additionally, the memory system may store an indication of whether the data is used for any access operations during a duration that the data is stored in the first portion of the cache. The memory system may transfer subsets of the data to the second portion of the cache if they are used for access operations during the duration.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: August 30, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nicola Colella, Antonino Pollio
  • Patent number: 11422935
    Abstract: A method of controlling a cache is disclosed. The method comprises receiving a request to allocate a portion of memory to store data. The method also comprises directly mapping a portion of memory to an assigned contiguous portion of the cache memory when the request to allocate a portion of memory to store the data includes a cache residency request that the data continuously resides in cache memory. The method also comprises mapping the portion of memory to the cache memory using associative mapping when the request to allocate a portion of memory to store the data does not include a cache residency request that data continuously resides in the cache memory.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 23, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Chintan S. Patel, Vydhyanathan Kalyanasundharam, Benjamin Tsien
  • Patent number: 11409661
    Abstract: A logical to physical (L2P) mapping component can determine whether an offset between a physical page address (PPA) and a logical block address (LBA) will be altered in response to writing data corresponding to the PPA and comprising at least one redundant array of independent NAND parity bit to a first level of a logical to physical (L2P) data structure or a second level of the L2P data structure, or both. The L2P mapping component can further cause an indication comprising at least two bits corresponding to the offset to be written to the first level of the L2P data structure or the second level of the L2P data structure, or both.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang
  • Patent number: 11403010
    Abstract: A plane selection method is provided, which is applied to a data storage medium including a plurality of planes, wherein each of the planes includes a plurality of blocks, each of the blocks includes a plurality of pages, and each of the pages which includes a plurality of data columns is divided into a plurality of chunks. The plane selection method includes steps of defining at least one data column having a largest number of error bits in a worst chunk as a bad column until a quantity of bad columns is used up, determining whether at least two planes are uncorrectable according to a distribution of the bad columns, and eliminating a record of the bad columns and banning a worse plane which had the most bad columns than other planes.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: August 2, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Sheng-Yuan Huang
  • Patent number: 11392504
    Abstract: Systems and methods for supporting memory page fault handling for network devices are disclosed. In one implementation, a processing device may receive, at a network interface device of a host computer system, an incoming packet from a network. The processing device may also select a first buffer from a plurality of buffers associated with a receiving queue of the network interface device. The processing device may attempt to store the incoming packet at the first buffer of the plurality of buffers. Responsive to receiving a notification that attempting to store the incoming packet at the first buffer encountered a page fault, the processing device may assign the first buffer to a wait queue of the network interface device. The processing device may further store the incoming packet at a second buffer of the plurality of buffers associated with the receiving queue.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: July 19, 2022
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 11386005
    Abstract: Disclosed are a memory system, a memory controller, and a method of operating a memory system. The memory system may control the memory device to store data into zones of memory blocks in the memory device by assigning each data to be written with an address subsequent to a most recently written address in a zone, store journal information including mapping information between a logical address and a physical address for one of the one or more zones in a journal cache, search for journal information corresponding to a target zone targeted to write data when mapping information for the target zone among the one or more zones is updated, and replace the journal information corresponding to the target zone with journal information including the updated mapping information.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: July 12, 2022
    Assignee: SK HYNIX INC.
    Inventor: Chan Ho Ha
  • Patent number: 11385820
    Abstract: Methods, systems, and devices for command batching for a memory sub-system are described. A memory sub-system can receive a plurality of commands for a plurality of transfer units of a memory sub-system and generate a list of the plurality of transfer units that includes pointers between the plurality of transfer units. The memory sub-system can store at least one pointer of the list in a shared memory that is shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list. The memory sub-system can send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory and retrieve the plurality of transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: July 12, 2022
    Assignee: Micron Technology, Inc.
    Inventors: John Paul Traver, Yun Li, Scheheresade Virani, Ning Zhao, Tom Victor Maria Geukens