Patents Examined by Sean D Rossiter
  • Patent number: 10809919
    Abstract: A storage cluster includes a plurality of storage nodes. Each of the plurality of storage nodes includes nonvolatile solid-state memory and each of the plurality of storage nodes is configured to cooperate with others of the plurality of storage nodes having differing storage capacities in applying erasure coding. The plurality of storage nodes are configured to distribute the user data and metadata throughout the plurality of storage nodes.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: October 20, 2020
    Assignee: Pure Storage, Inc.
    Inventors: John Martin Hayes, Par Anders Botes, John Colgrove, John D. Davis, Robert Lee, Joshua P. Robinson, Peter Vajgel
  • Patent number: 10809943
    Abstract: A data storage device includes a memory controller and a memory device. The memory controller includes multiple memory blocks, and each memory block includes multiple pages. The memory controller is coupled to the memory device and configured to access the memory device. In an initialization procedure of the data storage device, the memory controller is configured to determine whether a sudden power-off has occurred during a first write operation to write data to a first memory block, and when a sudden power-off is determined to have occurred during the first write operation, the memory controller is configured to select a second memory block that is and write data to the second memory block in a second write operation.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: October 20, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Chia-Chi Liang, Hsuan-Ping Lin
  • Patent number: 10802967
    Abstract: Embodiments described herein provide a general purpose graphics processor comprising a plurality of tiles, each tile of the plurality of tiles comprising at least one execution unit, a local cache, and a cache control unit, and a high bandwidth memory communicatively coupled to the plurality of tiles, wherein the high bandwidth memory is shared between the plurality of tiles. The cache control unit is to implement a partial write management protocol to receive a partial write operation directed to a cache line in the local cache, the partial write operation comprising write data, write the data associated with the partial write operation to the local cache when the cache line is in a modified state, and forward the write data associated with the partial write operation to the high bandwidth memory when the partial write operation triggers a cache miss or when the cache line is in an exclusive state or a shared state. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 13, 2020
    Assignee: INTEL CORPORATION
    Inventors: Joydeep Ray, James Valerio, Ben Ashbaugh, Lakshminarayanan Striramassarma
  • Patent number: 10802960
    Abstract: A flash medium access method, including selecting, by a controller, a target function queue from N function queues according to a predefined rule, where the target function queue is a non-empty queue, a flash medium in which a die associated with the target function queue is located is in an idle state, obtaining a basic instruction from the target function queue, determining, according to preset queue mapping information, the die associated with the target function queue, where the controller is connected to at least one flash medium, and the queue mapping information indicates that the N function queues are in a one-to-one mapping relationship with the N dies, generating, according to a preset signal generation rule, a time sequence signal corresponding to the basic instruction, and sending the time sequence signal to the flash medium in which the associated die is located.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: October 13, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Tao Li, Guanfeng Zhou, Sheng Li
  • Patent number: 10795824
    Abstract: Speculative data return in parallel with an exclusive invalidate request. A requesting processor requests data from a shared cache. The data is owned by another processor. Based on the request, an invalidate request is sent to the other processor requesting the other processor to release ownership of the data. Concurrent to the invalidate request being sent to the other processor, the data is speculatively provided to the requesting processor.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Deanna P. Berger, Christian Jacobi, Robert J. Sonnelitter, III, Craig R. Walters
  • Patent number: 10789184
    Abstract: In the present invention, computational efficiency degradation is suppressed when diagnosing a shared storage area in a vehicle control device in which a plurality of computing units are employed. This vehicle control device suppresses computational efficiency degradation by changing an access destination in a storage device while diagnosing a shared storage area that the storage device has.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: September 29, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Tsunamichi Tsukidate, Yusuke Abe, Takeshi Fukuda, Tomohito Ebina, Fumio Narisawa
  • Patent number: 10789175
    Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected profile from plural profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected profile for a selected least recently used (LRU) position in the cache.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: September 29, 2020
    Assignee: Mellanox Technologies Ltd.
    Inventors: Gilad Tal, Gil Moran, Miriam Menes, Gil Kopilov, Shlomo Raikin
  • Patent number: 10783078
    Abstract: In one aspect, a method includes splitting empty RAID stripes into sub-stripes and storing pages into the sub-stripes based on a compressibility score. In another aspect, a method includes reading pages from 1-stripes, storing compressed data in a temporary location, reading multiple stripes, determining compressibility score for each stripe and filling stripes based on the compressibility score. In a further aspect, a method includes scanning a dirty queue in a system cache, compressing pages ready for destaging, combining compressed pages in to one aggregated page, writing one aggregated page to one stripe and storing pages with same compressibility score in a stripe.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: September 22, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: David Meiri, Anton Kucherov, Vladimir Shveidel
  • Patent number: 10776112
    Abstract: Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 15, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles W. Gainey, Jr., Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Gustav E. Sittmann, III
  • Patent number: 10776009
    Abstract: A computer-implemented method, a computer program product, and a computer system for journaling on an appendable non-volatile memory module. A kernel receives a request for a write operation of a file on a disk. The kernel instructs a memory management unit to perform an access control list verification. The memory management unit determines whether a user associated with the write operation is permitted to write a filesystem journal onto a non-volatile dual in-line memory module, by performing the access control list verification. The memory management unit writes the filesystem journal onto the non-volatile dual in-line memory module, in response to that the user associated with the write operation is permitted to write the filesystem journal. The kernel writes the file onto the disk.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Breno H. Leitao, Juscelino Candido de Lima Junior, Carlos Eduardo Seo
  • Patent number: 10776214
    Abstract: A system and method for protecting desired data in a non-volatile dual in line memory module (NVDIMM) in a computer system. The system includes a basic input output system (BIOS). The non-volatile dual in line memory module (NVDIMM) is coupled to a memory bus. The NVDIMM includes a non-persistent memory and a persistent memory. A processor is coupled to the memory bus. When an update is applied to the basic input output system, desired data stored in the persistent memory of the NVDIMM is protected by disabling a NVDIMM backup function after a first power cycle immediately after the BIOS update. The backup function is enabled to restore the desired data to the non-persistent memory of NVDIMM from persistent memory after a second power cycle.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: September 15, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventor: Chun-Po Ma
  • Patent number: 10761728
    Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a command processor configured to generate a flush command in response to a flush request input from an external host and to assign a slot number corresponding to the flush command; a sequence generator configured to determine flush data to be stored in response to the flush command, and to generate a write sequence in which the flush data is to be stored based on a size of the flush data and an assigned device sequence of the plurality of memory devices; and a memory operation controller configured to control the plurality of memory devices to store the flush data in the plurality of memory devices.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: September 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Sung Kwan Hong, Yeong Sik Yi
  • Patent number: 10761851
    Abstract: The present disclosure provides a memory apparatus comprising a first set of storage blocks operating as a set of read storage blocks in a first computation layer and as a set of write storage blocks in a second computation layer, where the second computation layer follows the first computation layer. The memory apparatus also comprises a second set of storage blocks operating as a set of write storage blocks in the first computation layer and as a set of read storage blocks in the second computation layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 1, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Liang Han, Xiaowei Jiang, Jian Chen
  • Patent number: 10754585
    Abstract: A method for performing writing management in a memory device, the memory device, and the controller thereof are provided. The method may include: writing first partial data of even-page data into a non-volatile (NV) memory; transmitting a first set of commands without a confirmation command to the NV memory, to write the first partial data and second partial data of the even-page data into an internal buffer within the NV memory; transmitting a second set of commands and the confirmation command to the NV memory, to write the first partial data and the second partial data into a block of the NV memory; writing third partial data of odd-page data into the NV memory; and writing the first and the second partial data into an even page of another block of the NV memory, and writing the third and fourth partial data into an odd page of this block.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 25, 2020
    Assignee: Silicon Motion, Inc.
    Inventors: Wei-Lun Yan, Ming-Yen Lin, Chin-Pang Chang
  • Patent number: 10754799
    Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: August 25, 2020
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Ian Shaeffer
  • Patent number: 10754796
    Abstract: Systems and methods for providing technology that enhances memory protection between different portions of the user space memory of a particular computing process. An example method may comprise: creating a computing process comprising a first executable code and a second executable code; loading the first and second executable code into user space memory of the computing process, wherein the second executable code comprises driver code of a device; updating a first and second page table structures, wherein the first page table structure comprises mapping data for the first and second executable code and wherein the second page table structure comprises mapping data to access the device; providing, by the processor, an instruction enabling the computing process to switch to the second page table structure; and enabling the first executable code to execute using the first page table structure and the second executable code to execute using the second page table structure to access the device.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: August 25, 2020
    Assignee: Red Hat, Inc.
    Inventor: Michael Tsirkin
  • Patent number: 10747665
    Abstract: In an embodiment, a partition cost of one or more of the plurality of partitions and a data block cost for one or more data blocks that may be subjected to a garbage collection operation are determined. The partition cost and the data block cost are combined into an overall reclaim cost by specifying both the partition cost and the data block cost in terms of a computing system latency. A byte constant multiplier that is configured to modify the overall reclaim cost to account for the amount of data objects that may be rewritten during the garbage collection operation may be applied. The one or more partitions and/or one or more data blocks that have the lowest overall reclaim cost while reclaiming an acceptable amount of data block space may be determined and be included in a garbage collection schedule.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: August 18, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Shane Kumar Mainali, Rushi Srinivas Surla, Peter Bodik, Ishai Menache, Yang Lu
  • Patent number: 10740249
    Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Jason W. Brandt, Sanjoy K. Mondal, Richard A. Uhlig, Gilbert Neiger, Robert T. George
  • Patent number: 10732852
    Abstract: Techniques for request processing may include: receiving, at a data storage system, a plurality of requests from one or more clients, wherein the plurality of requests are in accordance with an application programming interface (API); collecting usage information regarding the plurality of requests; and periodically transmitting portions of the usage information to a data center. The usage information may include usage statistics regarding usage aspects of the API with respect to different types or classes of components in the data storage system. The usage information may be further analyzed for any suitable purpose such as to prioritize and identify existing features, services and/or commands for further development and improvement; identify unused or infrequently used features, commands, and/or parameters; and identify potential user interface enhancement.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: August 4, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Qiang Ma, James Odis Pendergraft, Hao Sun, Jichao Zhang
  • Patent number: 10725675
    Abstract: According to an embodiment, a management apparatus manages access to a plurality of types of storage units by a processing circuit. Each of the plurality of types of storage units includes a plurality of first regions, and each of the plurality of first regions includes a plurality of second regions. The management apparatus includes a circuitry configured to function as a management unit. The management unit manages a management table in which identification information of one or more of the plurality of first regions and access management information defining access information indicating whether or not each second region included in the one or more of the plurality of first regions is accessed by the processing circuit are associated with each other.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 28, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsunori Kanai, Yusuke Shirota