Patents Examined by Selim Ahmed
  • Patent number: 10242891
    Abstract: Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 26, 2019
    Assignee: Cerebras Systems Inc.
    Inventors: Jean-Philippe Fricker, Frank Jun, Paul Kennedy
  • Patent number: 10243056
    Abstract: A semiconductor device includes a field insulating film including a first region and a second region on a substrate, a recess in the first region of the field insulating film, a gate electrode on the second region of the field insulating film, and a gate spacer along a sidewall of the gate electrode and a sidewall of the recess.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: March 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Kwan Yu, Kyung Ho Kim, Dong Suk Shin
  • Patent number: 10236185
    Abstract: A method of forming patterns for a semiconductor device includes preparing a hardmask composition including a carbon allotrope, a spin-on hardmask (SOH) material, an aromatic ring-containing polymer, and a solvent, applying the hardmask composition to an etching target layer, forming a hardmask by heat-treating the applied hardmask composition, forming a photoresist pattern on the hardmask, forming a hardmask pattern by etching the hardmask using the photoresist pattern as an etching mask, and forming an etched pattern by etching the etching target layer using the hardmask pattern as an etching mask.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: March 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yool Kang, Kyoung-sil Park, Yun-seok Choi, Boo-deuk Kim, Ye-hwan Kim
  • Patent number: 10236408
    Abstract: The yield of a manufacturing process of a semiconductor device is increased. The productivity of a semiconductor device is increased. A first material layer is formed over a substrate, a second material layer is formed over the first material layer, and the first material layer and the second material layer are separated from each other, so that a semiconductor device is manufactured. In addition, a stack including the first material layer and the second material layer is preferably heated before the separation. The first material layer includes one or more of hydrogen, oxygen, and water. The first material layer includes a metal oxide, for example. The second material layer includes a resin (e.g., polyimide or acrylic). The first material layer and the second material layer are separated from each other by cutting a hydrogen bond.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: March 19, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masataka Sato, Naoki Ikezawa, Junpei Yanaka, Satoru Idojiri
  • Patent number: 10236441
    Abstract: A magnetoresistance effect element has a first ferromagnetic metal layer, a second ferromagnetic metal layer, and a tunnel barrier layer that is sandwiched between the first and second ferromagnetic metal layers, the tunnel barrier layer has a spinel structure in which cations are arranged in a disordered manner, and the tunnel barrier layer is expressed by a composition formula of (M1-xZnx)((T1)2-y(T2)y)O4 wherein M represents a non-magnetic divalent cation other than Zn, each of T1 and T2 represents a non-magnetic trivalent cation, and x and y represent a composition ratio in a region where composition ratios combined as follows ((1) to (5)) are vertexes, and the vertexes are connected by straight lines: (1) x=0.2, y=0.1, (2) x=0.8, y=0.1, (3) x=0.8, y=1.7, (4) x=0.6, y=1.7, and (5) x=0.2, y=0.7.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: March 19, 2019
    Assignee: TDK CORPORATION
    Inventor: Tomoyuki Sasaki
  • Patent number: 10217403
    Abstract: The disclosure provides a display apparatus. The display apparatus of the disclosure includes a substrate having a plurality of pixel regions, a plurality of active elements, a plurality of first signal lines and second signal lines, a plurality of ground signal lines and a plurality of light emitting diodes (LEDs). The plurality of ground signal lines are disposed on the substrate and arranged to alternate with the first signal lines. At least one LED has first and second electrodes. The first electrode of at least one LED is electrically connected with a corresponding active element. A second electrode of at least one LED is electrically connected with a corresponding ground signal line. At least two LEDs disposed in an identical pixel region is electrically connected with an identical ground signal line between two first signal lines adjacent to each other. The display apparatus of the disclosure has high resolution.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: February 26, 2019
    Assignee: Innolux Corporation
    Inventors: Chun-Hsien Lin, Chih-Yung Hsieh, Tsau-Hua Hsieh, Shu-Ming Kuo
  • Patent number: 10217643
    Abstract: A method of processing a target object is provided. The target object includes a first protrusion portion, a second protrusion portion, an etching target layer and a groove portion. The groove portion is provided on a main surface of the target object, provided on the etching target layer and defined by the first and the second protrusion portions. An inner surface of the groove portion is included in the main surface. In the method, a first sequence is repeatedly performed N times (N is an integer equal to or larger than 2). The first sequence includes (a) forming a protection film conformally on the main surface in a processing vessel of a plasma processing apparatus in which the target object is accommodated; and (b) etching a bottom portion of the groove portion with plasma of a gas generated within the processing vessel after the process a is performed.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: February 26, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Tabata, Yoshihide Kihara
  • Patent number: 10217676
    Abstract: A method for manufacturing a semiconductor device including a plurality of semiconductor chips includes steps of placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip, determining a distance between the first semiconductor chip and the second semiconductor chip, and determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: February 26, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinya Fukayama, Naoyuki Komuta, Hiroshi Watabe
  • Patent number: 10204784
    Abstract: One illustrative method disclosed herein includes, among other things, forming an initial patterned etch mask above a feature-formation etch mask, the initial patterned etch mask including a plurality of laterally spaced-apart features having a non-uniform spacing, and performing at least one first etching process to remove an entire axial length of at least one of the plurality of features so as to thereby form a modified final patterned etch mask comprised of a plurality of features with a uniform spacing that defines a feature-formation pattern. In this example, the method also includes performing at least one second etching process so as to form a patterned feature-formation etch mask comprising the feature-formation pattern and performing at least one third etching process so as to form a plurality of features in a first layer, the features being formed with the feature-formation pattern.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jinsheng Gao, Hui Zang, Haigou Huang
  • Patent number: 10204934
    Abstract: The embodiments of the present disclosure relate to an array substrate, a thin film transistor, methods for fabricating the same, and a display device. The method for fabricating the array substrate provided by the embodiments of the present disclosure comprises: forming an active layer on a substrate; forming a gate on the active layer; forming a first insulation layer on the gate; forming a light blocking portion on the first insulation layer, the light blocking portion being arranged above an edge portion of the gate, so that the light blocking portion blocks light entering the active layer from the edge portion of the gate.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: February 12, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Hongwei Tian, Yanan Niu, Liang Tang, Chaobo Zhang, Luopeng Chuo
  • Patent number: 10204935
    Abstract: A method for manufacturing a display device includes forming a first gate metal wire on a substrate, forming a first insulation layer that covers the first gate metal wire, forming a second gate metal wire on the first insulation layer, forming a second main insulation layer that covers the second gate metal wire, forming a second auxiliary insulation layer on the second main insulation layer, forming an exposed portion of an upper surface of the second main insulation layer by polishing the second auxiliary insulation layer, and forming a first data metal wire on the second main insulation layer and the second auxiliary insulation layer.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: February 12, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Jin Cho, Joon-Hwa Bae, Byoung Kwon Choo, Byung Hoon Kang, Kwang Suk Kim, Woo Jin Cho, Jun Hyuk Cheon
  • Patent number: 10199271
    Abstract: A structure and method for forming a self-aligned metal wire on a contact structure. The method for forming the self-aligned metal wire and contact structure may include, among other things, forming an initial contact structure above a substrate; forming a patterned mask on the initial contact structure, the mask including an opening; using the patterned mask to form an opening through the initial contact structure; forming a dielectric layer in the openings; removing the patterned mask to expose a remaining portion of the initial contact structure; and forming the metal wire on the remaining portion of the initial contact structure. The contact structure may include a vertical cross-sectional geometry including one of a trapezoid wherein a bottommost surface of the first contact structure is wider than an uppermost surface of the first contact structure, and a parallelogram. The metal wire may completely contact an uppermost surface of the contact structure.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Guillaume Bouche, Laertis Economikos, Lei Sun, Guoxiang Ning, Xunyuan Zhang
  • Patent number: 10199486
    Abstract: A semiconductor device 1 of an embodiment is provided, including an insulating substrate 2, conductive pattern parts 51, 52, 53, 54, and 55 formed on the insulating substrate, a GaN-HEMI 10 disposed on the conductive pattern part 51, and a GaN-HEMT 20 disposed on the conductive pattern part 52, wherein an imaginary line L1 of the GaN-HEMT 10 and an imaginary line L2 of the GaN-HEMT 20 intersect each other, a GaN gate electrode 23 of the GaN-HEMT 20 is electrically connected to the conductive pattern part 55 via a metal wire 6, and the metal wire 6 is perpendicular to a side 55 of the GaN-HEMT 20 and a conductive pattern side 55S of the conductive pattern part 55.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: February 5, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yuji Morinaga, Atsushi Kyutoku, Yoshihiko Kikuchi
  • Patent number: 10192921
    Abstract: A solid state imaging device having a light sensing section that performs photoelectric conversion of incident light includes: an insulating layer formed on a light receiving surface of the light sensing section; a layer having negative electric charges formed on the insulating layer; and a hole accumulation layer formed on the light receiving surface of the light sensing section.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: January 29, 2019
    Assignee: Sony Corporation
    Inventors: Itaru Oshiyama, Takashi Ando, Susumu Hiyama, Tetsuji Yamaguchi, Yuko Ohgishi, Harumi Ikeda
  • Patent number: 10186598
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a dummy gate structure over the base substrate; forming source/drain regions having source/drain doping ions in the base substrate at both sides of the dummy gate structure; forming a dielectric layer on the source/drain regions and covering the side surfaces of the dummy gate structure; removing the dummy gate structure to form an opening in the dielectric layer; performing one or more of a first ion implantation process, for implanting first barrier ions in the base substrate toward the source region to form a first barrier layer under the opening, and a second ion implantation process, for implanting second barrier ions in the base substrate toward the source region to form a second barrier layer under the opening; and forming a gate structure in the opening.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: January 22, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Meng Zhao
  • Patent number: 10181436
    Abstract: A lead frame includes leads including inner leads and outer leads. Each of the leads includes an inner lead and an outer lead. A tie bar extends so as to cross connecting points of the inner leads and the outer leads. The leads and the tie bar include a first surface, a second surface, and side surfaces. A plating layer is provided on the inner leads, the outer leads and the tie bar. A first non-plating region is provided between an edge in the first surface of the inner lead and an edge of the plating layer provided on the first surface of the inner lead. A second non-plating region is provided between an edge of the first surface on the inner lead side of the tie bar and an edge on the inner lead side of the plating layer provided on the first surface of the tie bar.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 15, 2019
    Assignee: SH MATERIALS CO., LTD.
    Inventor: Jun Fukuzaki
  • Patent number: 10177227
    Abstract: The present disclosure provides methods for forming horizontal gate-all-around (hGAA) structure devices. In one example, a method includes selectively and laterally etching a first group of sidewalls of a first layer in a multi-material layer, wherein the multi-material layer comprises repeating pairs of the first layer and a second layer, the first and the second layers having the first group and a second group of sidewalls respectively, the first group of sidewalls from the first layer exposed through openings defined in the multi-material layer and a group of inner spacers formed atop of the second group of sidewalls from the second layer, forming a recess from the first group of sidewalls of the first layer and defining a vertical wall inward from an outer vertical surface of the inner spacer formed atop of the second layers, and forming an epi-silicon layer from the recess of the first layer.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 8, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Naomi Yoshida, Lin Dong, Shiyu Sun, Myungsun Kim, Nam Sung Kim, Dimitri Kioussis, Mikhail Korolik, Gaetano Santoro, Vanessa Pena
  • Patent number: 10175546
    Abstract: Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a plurality of pixel structures. The pixel structure includes a gate electrode, a gate electrode insulating layer, an active layer, source and drain electrodes, and a passivation layer which are sequentially stacked. The pixel structure further includes a first electrode and a second electrode. The first electrode is located between the gate electrode insulating layer and the passivation layer, and electrically connected to one of the source electrode and the drain electrode. The second electrode is located above the passivation layer. A first via passing through the passivation layer is provided, and the second electrode is electrically connected to one of the source electrode and the drain electrode through the first via.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 8, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xingyou Luo, Peizhi Cai, Xi Chen, Lei Ma, Jinyu Li, Yanchen Li, Fengchun Pang, Xue Cao, Shaojun Hou
  • Patent number: 10170698
    Abstract: A method of forming a pillar includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A layer under the island of photoresist material is etched to establish a pillar defined by the island of photoresist material.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: January 1, 2019
    Inventors: Anthony J. Annunziata, Armand A. Galan, Steve Holmes, Eric A. Joseph, Gen P. Lauer, Qinghuang Lin, Nathan P. Marchack
  • Patent number: 10170573
    Abstract: A semiconductor device includes a substrate, a metal gate on the substrate, and a first inter-layer dielectric (ILD) layer around the metal gate. A top surface of the metal gate is lower than a top surface of the ILD layer thereby forming a recessed region atop the metal gate. A mask layer is disposed in the recessed region. A void is formed in the mask layer within the recessed region. A second ILD layer is disposed on the mask layer and the first ILD layer. A contact hole extends into the second ILD layer and the mask layer. The contact hole exposes the top surface of the metal gate and communicates with the void. A conductive layer is disposed in the contact hole and the void.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: January 1, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Ting Chiang, Jie-Ning Yang, Chi-Ju Lee, Chih-Wei Lin, Bo-Yu Su, Yen-Liang Wu, I-Fan Chang, Jui-Ming Yang, Wen-Tsung Chang