Patents Examined by Selim U Ahmed
  • Patent number: 11515264
    Abstract: A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: November 29, 2022
    Assignee: Infineon Technologies AG
    Inventors: Francisco Javier Santos Rodriguez, Alexander Breymesser, Erich Griebl, Michael Knabl, Matthias Kuenle, Andreas Moser, Roland Rupp, Hans-Joachim Schulze, Sokratis Sgouridis, Stephan Voss
  • Patent number: 11495664
    Abstract: A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: November 8, 2022
    Assignee: Adamantite Technologies LLC
    Inventor: Eric David Bauswell
  • Patent number: 11488923
    Abstract: A semiconductor device package includes a substrate, a silicon (Si) or silicon carbide (SiC) semiconductor die, and a metal layer on a surface of the semiconductor die. The metal layer includes a bonding surface that is attached to a surface of the substrate by a die attach material. The bonding surface includes opposing edges that extend along a perimeter of the semiconductor die, and one or more non-orthogonal corners that are configured to reduce stress at an interface between the bonding surface and the die attach material. Related devices and fabrication methods are also discussed.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: November 1, 2022
    Assignee: WOLFSPEED, INC.
    Inventors: Sung Chul Joo, Alexander Komposch, Brian William Condie, Benjamin Law, Jae Hyung Jeremiah Park
  • Patent number: 11469183
    Abstract: A method of manufacturing a semiconductor device includes mounting an interconnect chip to a redistribution layer structure and mounting a first, second, and third semiconductor chip to the redistribution layer structure, where the second semiconductor chip is interposed between the first and the third semiconductor chips, and the interconnect chip communicatively couples the first, second and third, semiconductor chips to one another.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: October 11, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Rahul Agarwal, Milind S. Bhagavat
  • Patent number: 11469166
    Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: October 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Fa Chen, Chen-Hua Yu
  • Patent number: 11447864
    Abstract: There is provided a method and apparatus to deposit a molybdenum comprising layer on a substrate by supplying a precursor comprising molybdenum(VI) dichloride dioxide and a first reactant comprising boron and hydrogen to the substrate in a reaction chamber to react and form the molybdenum layer. The first reactant comprising boron and hydrogen may be diborane.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: September 20, 2022
    Assignee: ASM IP Holding B.V.
    Inventor: Jeroen Fluit
  • Patent number: 11450547
    Abstract: A semiconductor device of an embodiment is manufactured by forming a first layer by applying a liquid containing silicon oxide particles onto a first substrate, performing a first heat treatment, forming a second layer including a first insulator on the upper surface and the side surfaces of the first layer, forming a third layer including an electronic circuit on the second layer, bonding a second substrate including a semiconductor circuit to the third layer, and separating the first substrate and the second substrate at the first layer.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: September 20, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Shinichi Nakao
  • Patent number: 11444187
    Abstract: A semiconductor device includes a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof, a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer, an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer, a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region, a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region, a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: September 13, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Kohei Shinsho
  • Patent number: 11430665
    Abstract: A method of manufacturing a semiconductor device may include forming a stack structure by alternately stacking sacrificial layers and interlayer insulating layers on a substrate, forming channel structures extending through the stack structure, forming openings extending through the stack structure, forming lateral openings by removing the sacrificial layers exposed by the openings, and forming gate electrodes in the lateral openings. Forming the gate electrodes may include supplying a source gas containing tungsten (W) wherein the source gas is heated to a first temperature and is supplied in a deposition apparatus at the first temperature, supplying a reactant gas containing hydrogen (H) subsequently to supplying the source gas, wherein the reactant gas is heated to a second temperature and is supplied in the deposition apparatus at the second temperature, and supplying a purge gas subsequently to supplying the reactant gas.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: August 30, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taisoo Lim, Kyungwook Park, Wangyup Ryu, Keun Lee, Changwoo Lee, Hauk Han
  • Patent number: 11430797
    Abstract: Disclosed are devices and methods having a programmable resistor and an on-package decoupling capacitor (OPD). In one aspect a package includes an OPD and a programmable resistor formed from at least one thin-film transistor (TFT). The programmable resistor is disposed in series with the OPD between a supply voltage (VDD) conductor and a ground conductor.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: August 30, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Abinash Roy, Bharani Chava
  • Patent number: 11430783
    Abstract: The electrostatic discharge (ESD) protection apparatus includes a first well, a second well, a first doping region, and a second doping region. The first well is disposed in a substrate having a first conductivity type, wherein the first well has a second conductivity type and the substrate is electrically connected to a first pad. The second well is disposed in the first well, wherein the second well has the first conductivity type. The first doping region is disposed in the second well, wherein the first doping region has the second conductivity type, and the first doping region is electrically connected to a second pad. The second doping region is disposed in the second well, wherein the second doping region has the first conductivity type.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: August 30, 2022
    Assignee: Faraday Technology Corp.
    Inventors: Chia-Ku Tsai, Tsung-Hsiao Lin
  • Patent number: 11424193
    Abstract: Disclosed herein is a substrate of a display panel, comprising: a support; a first alignment mark on the support; a first dielectric layer covering the first alignment mark; an auxiliary alignment mark aligned with the first alignment mark, wherein the auxiliary alignment mark comprises a recess into the first dielectric layer. Further disclosed herein is a display panel comprising the substrate, and a system comprising the display panel. Also disclosed herein is a method comprising: forming a first alignment mark on a support; forming a first dielectric layer covering the first alignment mark; and forming an auxiliary alignment mark aligned with the first alignment mark; wherein the auxiliary alignment mark comprises a recess into the first dielectric layer.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: August 23, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tao Ma, Chao Jiao
  • Patent number: 11424197
    Abstract: A package includes a semiconductor package including a semiconductor die and a first insulating encapsulation, a substrate, and a second insulating encapsulation. The first insulating encapsulation encapsulates the semiconductor die. The substrate includes a redistribution circuitry, wherein the substrate is electrically coupled to the semiconductor package through the redistribution circuitry. The second insulating encapsulation is disposed on and partially covers the substrate, wherein the substrate is sandwiched between the semiconductor package and the second insulating encapsulation.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chung-Hao Tsai, Chen-Hua Yu, Chun-Lin Lu, Han-Ping Pu, Kai-Chiang Wu
  • Patent number: 11424127
    Abstract: There is included (a) supplying a gas containing an organic ligand to a substrate; (b) supplying a metal-containing gas to the substrate; and (c) supplying a first reducing gas to the substrate, wherein after (a), a metal-containing film is formed on the substrate by performing (b) and (c) one or more times, respectively.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: August 23, 2022
    Assignee: KOKUSAI ELECTRIC CORPORATION
    Inventors: Arito Ogawa, Atsuro Seino
  • Patent number: 11417539
    Abstract: In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Su-Fei Lin, Hsu-Lun Liu, Chien-Pin Chan, Yung-Sheng Lin
  • Patent number: 11410982
    Abstract: A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yi Yang, Po-Yao Chuang, Shin-Puu Jeng
  • Patent number: 11410851
    Abstract: Methods for forming a metallic film on a substrate by cyclical deposition are provided. In some embodiments methods may include contacting the substrate with a first reactant comprising a non-halogen containing metal precursor comprising at least one of copper, nickel or cobalt and contacting the substrate with a second reactant comprising a hydrocarbon substituted hydrazine. In some embodiments related semiconductor device structures may include at least a portion of a metallic interconnect formed by cyclical deposition processes.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: August 9, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Katja Väyrynen, Mikko Ritala, Markku Leskelä
  • Patent number: 11411042
    Abstract: An image sensor includes a substrate including a photodiode and first and second floating diffusion nodes which are disposed to be spaced apart from left and right of the photodiode, respectively, by a predetermined distance; a first transfer gate disposed on the substrate to overlap at least partially with the photodiode and the first floating diffusion node; and a second transfer gate disposed on the substrate to overlap at least partially with the photodiode and the second floating diffusion node, wherein each of the first transfer gate and the second transfer gate includes a first gate dielectric layer which overlaps at least partially with the photodiode and a second gate dielectric layer which overlaps at least partially with the first or second floating diffusion node, and wherein a thickness of the first gate dielectric layer is larger than a thickness of the second gate dielectric layer.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: August 9, 2022
    Assignee: SK hynix Inc.
    Inventor: Jae Hyung Jang
  • Patent number: 11410910
    Abstract: Semiconductor devices including lids having liquid-cooled channels and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first integrated circuit die; a lid coupled to the first integrated circuit die, the lid including a plurality of channels in a surface of the lid opposite the first integrated circuit die; a cooling cover coupled to the lid opposite the first integrated circuit die; and a heat transfer unit coupled to the cooling cover through a pipe fitting, the heat transfer unit being configured to supply a liquid coolant to the plurality of channels through the cooling cover.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sheng-Tsung Hsiao, Jen Yu Wang, Chung-Jung Wu, Tung-Liang Shao, Chih-Hang Tung
  • Patent number: 11401602
    Abstract: Methods of depositing a metal film with high purity are discussed. A catalyst enhanced CVD process is utilized comprising an alkyl halide catalyst soak and a precursor exposure. The precursor comprises a metal precursor having the general formula (I): M-L1(L2)y, wherein M is a metal, L1 is an aromatic ligand, L2 is an aliphatic ligand, and y is a number in the range of from 2 to 8 to form a metal film on the substrate surface, wherein the L2 comprises 1,5-hexdiene, 1,4-hexadiene, and less than 5% of 1,3-hexadiene. Selective deposition of a metal film with high purity on a metal surface over a dielectric surface is described.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: August 2, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Byunghoon Yoon, Seshadri Ganguli, Xi Cen