Abstract: A thin film transistor and method of making the same, the thin film transistor including: a substrate; a word line disposed on the substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region disposed between the source and drain regions and overlapping with the word line in a vertical direction perpendicular to a plane of the substrate; a hydrogen diffusion barrier layer overlapping with the channel region in the vertical direction; a gate dielectric layer disposed between the channel region and the word line; and source and drain electrodes respectively electrically coupled to the source and drain regions.

Abstract: A solid-state image pickup device includes a plurality of pixels, a pixel connection section, and a pixel reset section. The plurality of pixels each include a photoelectric conversion section that generates a charge according to irradiated light, a charge holding section that holds the generated charge, and a signal generation section that generates as an image signal a signal according to the held charge. The pixel connection section conducts between charge holding sections of the plurality of pixels and thereby allows each of the charge holding sections of the plurality of pixels to hold the charge that has been generated by the photoelectric conversion section of one pixel of the plurality of pixels. The pixel reset section discharges and resets the charge of the respective charge holding sections of the plurality of pixels when the pixel connection section conducts between the respective charge holding sections of the plurality of pixels.

Abstract: A method for forming hermetic seals between the cap and sub-mount for electronic and optoelectronic packages includes the formation of metal mounds on the sealing surfaces. Metal mounds, as precursors to a metal hermetic seal between the cap and sub-mount of a sub-mount assembly, facilitates the evacuation and purging of the volume created within cap and sub-mount assemblies prior to formation of the hermetic seal. The method is applied to discrete cap and sub-mount assemblies and also at the wafer level on singulated and non-singulated cap and sub-mount wafers. The method that includes the formation of the hermetic seal provides an inert environment for a plurality of electrical, optoelectrical, and optical die that are attached within an enclosed volume of the sub-mount assembly.

Abstract: An integrated circuit includes a solder pad which includes, in a superposition of metallization levels, an underlying structure formed by a network of first regular metal tracks that are arranged for reinforcing the mechanical strength of the underlying structure and electrically connecting between an upper metallization level and a lower metallization level of the underlying structure. The underlying structure further includes a detection electrical path formed by second metal tracks passing between the first metal tracks in the metallization levels, the detection electrical path having an input terminal and an output terminal. Electrical sensing of the detection electrical path is made to supply a measurement which is indicative of the presence of cracks in the underlying structure.

Abstract: In view of the problem that a reduced thickness of an EL film causes a short circuit between an anode and a cathode and malfunction of a transistor, the invention provides a display device that has a light emitting element including an electrode and an electroluminescent layer, a wire electrically connected to the electrode of the light emitting element, a transistor provided with an active layer including a source, a drain and a channel forming region, and a power supply line electrically connected to one of the source and the drain of the transistor, wherein the wire is electrically connected to the other of the source and the drain of the transistor, and the width of a part of the electrode in the vicinity of a portion where the electrode is electrically connected to the wire is smaller than that of the electrode in the other portion.

Abstract: A silicon semiconductor wafer is transported into a chamber, and preheating of the semiconductor wafer is started in a nitrogen atmosphere by irradiation with light from halogen lamps. When the temperature of the semiconductor wafer reaches a predetermined switching temperature in the course of the preheating, oxygen gas is supplied into the chamber to change the atmosphere within the chamber from the nitrogen atmosphere to an oxygen atmosphere. Thereafter, a front surface of the semiconductor wafer is heated for an extremely short time period by flash irradiation. Oxidation is suppressed when the temperature of the semiconductor wafer is relatively low below the switching temperature, and is caused after the temperature of the semiconductor wafer becomes relatively high. As a result, a dense, thin oxide film having good properties with fewer defects at an interface with a silicon base layer is formed on the front surface of the semiconductor wafer.

Abstract: Various examples provide a semiconductor patch. The patch includes a glass core having first and second opposed major surfaces extending in an x-y direction. The patch further includes a conductive via extending from the first major surface to the second major surface substantially in a z-direction. The patch further includes a bridge die embedded in a dielectric material in communication with the conductive via. The patch further includes an overmold at least partially encasing the glass core.

Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.

Abstract: Systems, methods, and apparatus including conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices. One memory device comprises arrays of vertically stacked memory cells, having multiple multi-direction conductive lines arrays of vertically stacked memory cells, including a vertical stack of layers formed from repeating iterations of a group of layers, the group of layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having a conductive line formed in a horizontal plane therein, and the vertical stack of layers having multiple multi-direction conductive lines in an interconnection region with a first portion of the interconnection region formed in an array region and a second portion formed in a conductive line contact region that is spaced from the array region.

Abstract: A device includes a first transistor over a substrate, a second transistor disposed over the first transistor, and a memory element disposed over the second transistor. The second transistor includes a channel layer, a gate dielectric layer surrounding a sidewall of the channel layer, and a gate electrode surrounding a sidewall of the gate dielectric layer.

Abstract: A power module can include a casing mounted to a baseplate that contains a substrate with circuitry. The circuitry can include pins for coupling signals to/from the circuitry. These pins can extend through a cover portion of the casing so that an electronic substrate, such as a printed circuit board (PCB) can be press-fit onto the pins. When press-fit, the electronic substrate is supported and positioned by support pillars that extend from the base plate to above the cover portion of the casing. If the pins and the support pillars have different coefficients of thermal expansion, damage to connection points between the pins and the circuitry may occur. Here, a power module is disclosed that has thermally matched pins and support pillars so that when the system is thermally cycled over a range of temperatures, the connection points are not damaged by forces induced by thermal expansion.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: A semiconductor package substrate includes an encapsulated interconnect on a land side of the substrate. The encapsulated interconnect includes an integral metallic structure that has a smaller contact end against the semiconductor package substrate, and a larger contact end for board mounting.

Abstract: A complementary transistor is constituted of a first transistor TR1 and a second transistor TR2, active regions 32, 42 of the respective transistors are formed by layering first A layers 33, 43 and the first B layers 35, 45 respectively, surface regions 201, 202 provided in a base correspond to first A layers 33, 43 respectively, first B layers 35, 45 each have a conductivity type different from that of the first A layers 33, 43, and extension layers 36, 46 of the first B layer are provided on insulation regions 211,212 respectively.

Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate.

Abstract: An integrated circuit interconnect structure includes a first interconnect in a first metallization level and a first dielectric adjacent to at least a portion of the first interconnect, where the first dielectric having a first carbon content. The integrated circuit interconnect structure further includes a second interconnect in a second metallization level above the first metallization level. The second interconnect includes a lowermost surface in contact with at least a portion of an uppermost surface of the first interconnect. A second dielectric having a second carbon content is adjacent to at least a portion of the second interconnect and the first dielectric. The first carbon concentration increases with distance away from the lowermost surface of the second interconnect and the second carbon concentration increases with distance away from the uppermost surface of the first interconnect.

Abstract: A method for producing electronic devices includes fixing a die that includes an electronic component with integral contacts to a dielectric substrate. After fixing the die, a conductive trace is printed over both the dielectric substrate and at least one of the integral contacts, so as to create an ohmic connection between the conductive trace on the substrate and the electronic component.

Abstract: A method of manufacturing an electronic component module includes a sacrificial-body arrangement step of disposing a sacrificial body on a first principal surface of a support, the support including the first principal surface and a second principal surface, the sacrificial body being smaller than the first principal surface when viewed in a thickness direction of the support, a resin molding step of molding a resin structure on the first principal surface so as to cover the sacrificial body disposed on the first principal surface, a recess forming step of forming a recess in the resin structure by removing the sacrificial body, a wiring-layer forming step of forming a wiring layer on a side surface of the recess and on a principal surface of the resin structure, the principal surface connecting with the side surface, and a component mounting step of mounting an electronic component in the recess.

Abstract: In one example, an electronic device, comprises a substrate, comprising a first dielectric having a top surface and a bottom surface, and a first conductor in the first dielectric and comprising a first via and a first trace over the first via. The first trace comprises a first trace sidewall and a first trace base, and the first via comprises a first via sidewall. The first conductor comprises a first arcuate vertex between the first trace sidewall and the first trace base, and a second arcuate vertex between the first via sidewall and the first trace base, an electronic component over the top surface of the substrate, and an encapsulant over the top surface of the substrate and contacting a lateral side of the electronic component. Other examples and related methods are also disclosed herein.

Abstract: An integrated substrate, an electronic assembly, and manufacturing methods thereof are provided. The integrated substrate structure includes a coarse redistribution structure, fine redistribution segments, and conductive connectors. The coarse redistribution structure includes a coarse dielectric layer and a coarse circuitry embedded therein. The fine redistribution segments disposed over the coarse redistribution structure and disposed side by side and apart from one another. The respective fine redistribution segment includes a fine dielectric layer thinner than the coarse dielectric layer, and a fine circuitry embedded in the fine dielectric layer. The fine circuitry includes a dimension and a pitch finer than those of the coarse circuitry, and a layout density of the fine circuitry is denser than that of the coarse circuitry.