Abstract: A circuit has at least one amplifier and a signal routing device such as one or more switches, and an array of antenna elements from which some subset must be enabled and processed at a time. The antenna elements can be grouped in accordance with an organization scheme (e.g., rows, columns) to enable more flexibility in selecting and routing the signals. The system is used to create one or more beams, which can be pointed (steered) to a wide range of directions by means of selecting one or more feed antennas in a switched-feed antenna without including full receive and transmit circuitry (DSP, frequency conversion) for each feed in the array. In this case, minimizing the number of DSP chains is desirable to reduce the cost, power, and complexity of the antenna. The resulting beam(s) can be combined and manipulated to support multiple users, track several targets, increase operational range, increase radar resolution, or data-rate in communications.

Abstract: Energy and a control signal may be provided using a coupled power and control cable. The coupled power and control cable may comprise a power cable, a control cable, and an overall jacket. The power cable may be connected between a switch and a fixture and may provide energy to the fixture from the switch. The control cable may be connected between the control circuit and the fixture and may provide the control signal to the fixture from the control circuit. The power cable and the control cable maybe disposed beneath the overall jacket.

Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.

Abstract: A microstrip antenna corresponds to a rectangular resonator. The resonator has first and second sides being parallel to a first direction and having a length corresponding to 3/2 wavelength, and has a shape notched from each of the first and second sides toward a center of the resonator. The antenna includes: a first portion constituting a periphery of the notched shape; and second and third portions facing each other across the first portion. The notched shape allows the first portion to contribute to a radiation characteristic. The first, second, and third portions each have a length corresponding to ½ wavelength in the first direction. The first portion has a width in the second direction that is narrower because of the notched shape than that of the second and third portions. The second or third portion is provided with a feeding point.

Abstract: An integrated base station antenna includes a feed board having a plurality of columns of radiating elements mounted thereon and a plurality of phase shifters coupled to the plurality of columns of radiating elements mounted on a same side of the feed board as the plurality of columns of radiating elements.

Abstract: A load control device is configured to generate a control signal having a desired magnitude for controlling a load regulation device adapted to control the power delivered to an electrical load. The load control device may comprise a control terminal arranged to provide the control signal to the load regulation device, a communication circuit for generating the control signal, and a control circuit configured to generate an output signal that is provided to the communication circuit. The communication circuit may be characterized by non-linear operation. The control circuit may adjust the magnitude of the output signal in response to the difference between the magnitude of the control signal and the desired magnitude to adjust the magnitude of the control signal towards the desired magnitude. The control circuit may also be configured to determine if an incompatible load regulation device is coupled to the load control device.

Abstract: A scanning antenna includes a transmission and/or reception region including a plurality of antenna units and a non-transmission and/or reception region other than the transmission and/or reception region.

Abstract: An improved electrical circuit for logic output level shifting using SiC JFETs with resistors on the input, inverting, stage and using diode degenerated JFET sources in the output stage.

Abstract: Embodiments of the present disclosure relate to a coupling component, a microwave device and an electronic device. The coupling component includes a first ground electrode, a first dielectric layer, a first transmission line, a second dielectric layer, a second ground electrode, a first substrate, a second transmission line, a second substrate and a third ground electrode which are sequentially stacked. Each of the first to third electrodes has a slot, and orthographic projections of the slots on the first dielectric layer overlap. An orthographic projection of a coupling end of the first transmission line on the first dielectric layer overlaps an orthographic projection of the slot of the second ground electrode on the first dielectric layer. An orthographic projection of a coupling end of the second transmission line on the first dielectric layer overlaps the orthographic projection of the slot of the second ground electrode.

Abstract: Methods and apparatus for controlling current to an LED light source in a lighting device are described. In some embodiments, a warm dim light output is achieved. In an exemplary embodiment, a light emitting diode (LED) circuit includes two or more circuit branches coupled in parallel across a two terminal direct current (DC) voltage input including a positive input terminal and a negative input terminal; each of the two or more circuit branches including a set of light emitting diodes, each of said set of light emitting diodes including at least one light emitting diode; and at least one of said circuit branches including a current control circuit that controls the current passing through each of said two or more circuit branches.

Abstract: An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

Abstract: It is disclosed an antenna array comprising a number of radiating elements and a supporting elongated flat printed circuit board (PCB) having a substrate and two opposite faces. Each radiating element is attached to the PCB; each radiating element is dipole-like and has a respective axis of symmetry; the axes of symmetry are aligned along a direction parallel to a longitudinal axis of the PCB and lie on a longitudinal plane parallel to a longitudinal center plane of the PCB and located between the opposite faces; the PCB comprises at least one conductive trace on one of the faces, the conductive trace acting as a ground plane; and for each radiating element, the PCB carries a respective feeding line to provide a feeding signal to the radiating element at a feed point located on the PCB and substantially belonging to the axis of symmetry.

Abstract: A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

Abstract: A scalable, distributed load control system for home automation based on a network of microphones may include control devices (e.g., load control devices) that may include microphones for monitoring the system and communicating audio data to a cloud server for processing. The control devices of the load control system may receive a single voice command and may be configured to choose one of the load control devices to transmit the voice command to the cloud server. The load control devices may be configured to receive a voice command, control a connected load according to the voice command if the voice command is a validated command, and transmit the voice command to a voice service in the cloud if the voice command is not a validated command. The voice service to which the load control devices transmit audio data to may be selectable.

Abstract: A signal transmitting and receiving apparatus including: a first on-die termination circuit connected to a first pin through which a first signal is transmitted or received and, when enabled, the first on-die termination circuit is configured to provide a first termination resistance to a signal line connected to the first pin; a second on-die termination circuit connected to a second pin through which a second signal is transmitted or received and, when enabled, the second on-die termination circuit is configured to provide a second termination resistance to a signal line connected to the second pin; and an on-die termination control circuit configured to independently control an enable time and a disable time of each of the first on-die termination circuit and the second on-die termination circuit.

Abstract: Certain aspects provide methods and apparatus for in-memory convolution computation. An example circuit for such computation generally includes a memory cell having a bit-line and a complementary bit-line and a computation circuit coupled to a computation input node of the circuit and at least one of the bit-line or the complementary bit-line. In certain aspects, the computation circuit comprises a counter, an NMOS transistor coupled to the memory cell, and a PMOS transistor coupled to the memory cell, drains of the NMOS and PMOS transistors being coupled to the counter.

Abstract: Technologies directed to a hybrid-feed network of a parallel feed network and series-fed sub-arrays are described. The hybrid-feed network includes a parallel feed network and multiple groups of series-fed tiles, each tile including a beamforming integrated circuit (IC) and a set of antenna elements.

Abstract: Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.

Abstract: In embodiments of the present disclosure, there is provided an approach for neural network model compression based on bank-balanced sparsity. In embodiments of the present disclosure, a set of weight parameters, such as a weight matrix, in a neural network is divided into a plurality of equal-sized banks in terms of number of elements, and then all of the equal-sized banks are pruned at the same sparsity level. In this way, each pruned bank will have the same number of non-zero elements, which is suitable for hardware speedup. Moreover, since each bank is pruned independently in a fine granularity, the model accuracy can be ensured. Thus, according to embodiments of the present disclosure, the neural network compression method based on bank-balanced sparsity can achieve both high model accuracy and high hardware speedup.

Abstract: A magneto-electric (ME) majority gate device includes a conducting device and a plurality of ME transistors coupled to the conducting device. In one implementation, the plurality of ME transistors include a ME AND gate device with downward interface polarization, a ME-transmission gate device with downward interface polarization, and a ME-XNOR gate device. In another implementation, the plurality of ME transistors is five single-input ME-FETs.