Abstract: A method for generating a test sequence for a fault in a sequential circuit to provide high fault coverage. In one embodiment (FIG. 1), a circuit state, which a system fails to justify, is stored as an illegal state in a step 107. In a step 103, a target fault is selected. In a step 104, the system performs its fault propagation processing to generate a test sequence and propagate the target fault from a fault location to any external output pin in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation. In a step 105, the system performs its state initialization processing to generate a test sequence and transfer the state of the circuit from its initial state to a state when the fault was sensitized in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation.