Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain indium and monolayers that contain molybdenum are deposited onto a substrate and subsequently processed to form molybdenum-doped indium oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.

Abstract: A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

Abstract: A package structure of photodiode and a forming method of the same are provided. The method includes providing a heat-dissipation plate; placing a circuit board on the heat-dissipation plate, the circuit board having an opening exposing a top surface of the heat-dissipation plate and a first contact pad located on a peripheral area of the opening; placing a carrier with a metal cladding surface into the opening, the carrier connecting the top surface of the heat-dissipation plate; placing a photodiode chip on the carrier wherein the bottom area of the photodiode chip is less than the metal cladding surface such that a portion of the metal cladding surface is exposed; and electrically connecting the exposed metal cladding surface to the first contact pad.

Abstract: A micropattern is joined to a substrate (W1) by: a first group of covering step and micropattern forming step by etching in a transfer step; and a second group of covering step and micropattern forming step by etching in the transfer step.

Abstract: Formulations and methods of making semiconductor devices and solar cell contacts are disclosed. The invention provides a method of making a semiconductor device or solar cell contact including ink-jet printing onto a silicon wafer an ink composition, typically including a high solids loading (20-80 wt %) of glass frit and preferably a conductive metal such as silver. The wafer is then fired such that the glass frit fuses to form a glass, thereby forming a contact layer to silicon.

Abstract: An active solid heatsink device and fabricating method thereof is related to a high-effective solid cooling device, where heat generated by a heat source with a small area and a high heat-generating density diffuses to a whole substrate using a heat conduction characteristic of hot electrons of a thermionic (TI) structure, and the thermionic (TI) structure and a thermo-electric (TE) structure share the substrate where the heat diffuses to. Further, the shared substrate serves as a cold end of the TE structure, and the heat diffusing to the shared substrate is pumped to another substrate of the TE structure serving as a hot end of the TE structure.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a layer over a substrate. The method includes forming a first opening in the layer that exposes a first region of the substrate. The method includes removing a first oxidation layer formed over the first region through a first sputtering process. The method includes filling the first opening with a conductive material. The method includes forming a second opening in the layer that exposes a second region of the substrate, the second region being different from the first region. The method includes removing a second oxidation layer formed over the second region through a second sputtering process. One of the first and second sputtering processes is more powerful than the other.

Abstract: FinFET end-implanted-semiconductor structures and methods of manufacture are disclosed herein. The method includes forming at least one mandrel on a silicon layer of a substrate comprising an underlying insulator layer. The method further includes etching the silicon layer to form at least one silicon island under the at least one mandrel. The method further includes ion-implanting sidewalls of the at least one silicon island to form doped regions on the sidewalls. The method further includes forming a dielectric layer on the substrate, a top surface of which is planarized to be coplanar with a top surface of the at least one mandrel. The method further includes removing the at least one mandrel to form an opening in the dielectric layer. The method further includes etching the at least one silicon island to form at least one fin island having doped source and drain regions.

Abstract: Apparatus and methods are provided for integrally packaging semiconductor IC (integrated circuit) chips with antennas having one or more radiating elements and tuning elements that are formed from package lead wires that are appropriated shaped and arranged to form antenna structures for millimeter wave applications.

Abstract: A method for manufacturing a semiconductor device provided with a circuit capable of high speed operation while the manufacturing cost is reduced.

Abstract: A non-volatile memory device contains a three dimensional stack of horizontal diodes located in a trench in an insulating material, a plurality of storage elements, a plurality of word lines extending substantially vertically, and a plurality of bit lines. Each of the plurality of bit lines has a first portion that extends up along at least one side of the trench and a second portion that extends substantially horizontally through the three dimensional stack of the horizontal diodes. Each of the horizontal diodes is a steering element of a respective non-volatile memory cell of the non-volatile memory device, and each of the plurality of storage elements is located adjacent to a respective steering element.

Abstract: An evaluation area of an evaluation object wafer is concentrically divided in a radial direction, an upper limit value to the number of COPs is set in each divided evaluation segment, and an acceptance determination of the single-crystal silicon wafer is made using the upper limit value as a criterion. Thereby, a quantitative and objective COP evaluation can be made, and a proper determination is made based on a clear criterion. The evaluation method of the present invention can sufficiently deal with automation of the COP evaluation (inspection) and the higher-quality wafer in the near future, and the evaluation method can be widely applied to production of the single-crystal silicon wafer and production of a semiconductor device.

Abstract: A semiconductor chip package and a method for manufacturing thereof includes sequentially forming upper dielectric layer patterns and lower dielectric patterns over a substrate to expose an underlying metal line such that the lower dielectric layer patterns overlap the metal line, positioning a solder ball over and contacting the lower dielectric layer patterns such that the solder ball does not contact the metal line, and then placing the solder ball in a contacting position over the metal line by performing an etching process on the lower dielectric layer patterns. Therefore, no cracks occur on the chip pads so that there is no concern of short phenomenon generated in the terminal.

Abstract: According to a crystallization method, in the crystallization by irradiating a non-single semiconductor thin film of 40 to 100 nm provided on an insulation substrate with a laser light, a light intensity distribution having an inverse peak pattern is formed on the surface of the substrate, a light intensity gradient of the light intensity distribution is controlled, a crystal grain array is formed in which each crystal grain is aligned having a longer shape in a crystal growth direction than in a width direction and having a preferential crystal orientation (100) in a grain length direction, and a TFT is formed in which a source region and a drain region are formed so that current flows across a plurality of crystal grains of the crystal grain array in the crystal growth direction.

Abstract: Programmable resistive RAM cells have a resistance that depends on the size of the contacts. Manufacturing methods and integrated circuits for lowered contact resistance are disclosed that have contacts of reduced size.

Abstract: A semiconductor device includes a semiconductor substrate, a first transistor including a first gate electrode, a first diffusion region, and a second diffusion region respectively formed above the semiconductor substrate, second transistor including a second gate electrode, the first diffusion region, and a third diffusion region respectively formed above the semiconductor substrate, and a node electrode formed above the first diffusion layer, and coupled thereto. The first gate electrode and the second gate electrode are formed separately at respective side walls of the node electrode.

Abstract: The present invention provides a semiconductor light-emitting device that includes a compound semiconductor layer formed by laminating a first clad layer, a light-emitting layer and a second clad layer, a plurality of first ohmic electrodes formed on the first clad layer, a plurality of second ohmic electrodes formed on the second clad layer, a transparent conductive film that is formed on the first clad layer of the compound semiconductor layer and is conductively connected to the first ohmic electrodes, a bonding electrode formed on the transparent conducting film, and a support plate that is positioned on the second clad layer side of the compound semiconductor layer and is conductively connected to the second ohmic electrodes.

Abstract: A semiconductor device and an optical print head, an image forming apparatus that has the semiconductor device are supplied capable of reduce occurrence probability of defect. The semiconductor device is formed by using semiconductor thin film bonded on the substrate, and includes a covering layer that covers at least one part region of the semiconductor thin film and covers at least one part of electroconductive member connecting with the semiconductor thin film.

Abstract: This invention pertains to methods and systems for fabricating semiconductor devices. One aspect of the present invention is a method of depositing a gapfill copper layer onto a barrier layer for semiconductor device metallization. In one embodiment, the method includes forming the barrier layer on a surface of a substrate and subjecting the barrier layer to a process condition so as to form a removable passivated surface on the barrier layer. The method further includes removing the passivated surface from the barrier layer and depositing the gapfill copper layer onto the barrier layer. Another aspect of the present invention is an integrated system for depositing a copper layer onto a barrier layer for semiconductor device metallization.