Abstract: A high speed, accurate AD converter operable at low supply voltage, even with low gain amplifiers, particularly for a serial-parallel or pipelined AD converter, has a sub AD converter in each block of the second and subsequent stages provided with an adjuster for adjusting the full scale reference voltage in accordance with the gain of the error amplifier of the preceding stage. Analog switches are rendered immune to low operating voltage by being supplied separate voltage higher than the supply voltage of the other components in their circuit.

Abstract: A variable length code (VLC) decoding apparatus disclosed herein has an interface circuit 10 wherein an input bit stream is fed. The interface circuit 10 includes a plurality of window registers for directly extracting the decoding objective bit stream from the input bit stream. Each of the window registers has 2.sup.n -bit storage locations for storing an bit stream shifted by 1 bit from that of its adjacent window registers. Therefore, the VLC decoding apparatus advantageously achieves a high speed for decoding operation through the use of a plurality of window registers for directly extracting a next undecoded sequence of an input bit stream.

Abstract: A sampled signal integrator is provided comprising: an amplifier; two pairs of capacitors, the first pair of capacitors being coupled between the input and output terminals of the amplifier in a conventional negative feedback configuration, and the second pair of capacitors being coupled to the input terminals of the amplifier by a first pair of switches and likewise being coupled to a Voltage source by a second pair of switches; the two pairs of switches being further cross-coupled or synchronized to accomplish double-rate integration; and a voltage bias coupled in shunt with each of the input terminals of the amplifier to thereby provide a common mode bias to the integrator. Likewise, in another embodiment of the invention, the output signals of a sampled signal integrator configured so as to accomplish double-rate integration may be modulated and decimated to reduce or remove DC or low frequency noise.

Abstract: In an encoding side, an estimate of input data is generated. An estimation error which is equal to a difference between the estimate and the input data is calculated. The estimation error is classified, thereby generating a category index indicative of a category corresponding to the estimation error. The input data is divided by a divisor, and a remainder of a result of the dividing is generated. The divisor is equal to a given value which is greater than a difference between an upper limit value and a lower limit value defining a range of the category. The category index and the remainder are encoded into corresponding codes which are outputted. In a decoding side, input data is decoded into a category index and a remainder. An estimate is generated from previous output data. A divisor is generated in accordance with the category index. An offset is generated in accordance with the divisor and the estimate. The offset is equal to the divisor multiplied by an integer.

Abstract: In a sampling rate converter for converting a sampling frequency L of a digital signal to a sampling frequency M (L:M conversion) or for converting a sampling frequency M of a digital signal to a sampling frequency L (M:L conversion), the same filter coefficients are utilized and a constant predetermined DC gain is maintained for both conversions. An over-sampler multiplies the sampling frequency L or M by M or L, respectively, during the L:M conversion and the M:L conversion, respectively. A filter, which receives the output of the over-sampler, restricts the frequency band of the output.

Abstract: The invention is a dictionary initialization scheme adaptive to changes in the type and structure of input data. The compression ratio is increased by minimizing the number of data entries used to represent single characters in the input data. By using fewer codes than what is normally used to represent characters in an array of input data, the dictionary can have fewer entries than the alphabet size. A further aspect of the invention implements a type of run-length encoding in the LZ methodology which exploits the redundant structure existing in the compressed stream in the presence of a long run. Some of the codewords in the compressed stream are deleted but can be recovered at the decompression site. The foregoing LZE method is used alone, or used in combination with other methods to form a compression scheme that is especially useful for transmitting network packets.

Abstract: A method and apparatus are provided for decoding variable length codewords carried in data blocks. A first buffer is loaded with a succession of data blocks. A second buffer is loaded with a first data block from the first buffer during a decoding cycle. The variable length codewords from the first data block in the second buffer are decoded to recover information. The process continues, with the second buffer being loaded with one data block at a time to successively decode new data blocks during successive decoding cycles.

Abstract: A mixed analog and digital integrated circuit with features which are especially useful for application as a front end for physiological signal instrumentation such as electrocardiographs, electromyographs, and electroencephalographs. The integrated circuit has 5 signal channels, each with analog amplification and analog to digital conversion. The channels can be configured for various combinations of input signal amplification, input signal summation, analog output driving, and AC impedance measurement. The integrated circuit has 2 digital serial input lines and 2 digital serial output lines, all designed for direct connection to optical couplers. Channel configuration, gain, and other parameters are externally controllable by a serial digital input signal. Up to 6 compatible devices can be serially connected in a chain.

Abstract: A method and apparatus for decoding a specially encoded bit stream without the use of an external clock. A bit stream is encoded so that the relative lengths of the pulse widths between the transitions in the bit stream are indicative of the type bit being transmitted. A decoder receives the bit stream, measures the lengths of the pulses between the transitions, determines the type of bit by comparing the lengths, and stores the bit in a shift register. The bits can then be output in parallel form.

Abstract: A class of lossless data compression algorithms use a memory-based dictionary of finite size to facilitate the compression and decompression of data. To reduce the loss in data compression caused by dictionary resets, a standby dictionary is used to store a subset of encoded data entries previously stored in a current dictionary. In a second aspect of the invention, data is compressed/decompressed according to the address location of data entries contained within a dictionary built in a content addressable memory (CAM). In a third aspect of the invention, the minimum memory/high compression capacity of the standby dictionary scheme is combined with the fast single-cycle per character encoding/decoding capacity of the CAM circuit. The circuit uses multiple dictionaries within the storage locations of a CAM to reduce the amount of memory required to provide a high data compression ratio.

Abstract: A decoder circuit for generating mask patterns on a plurality of output terminals in response to multibit binary input number is described using a plurality of two-input multiplexers arranged in parallel paths to form one stage or as a tree structure consisting of several cascaded stages of binary or higher order and controlled by functions of the bits of an input number to produce a logic "1" voltage on a number of output terminals equal to the input number and a logic "0" voltage on the remaining output terminals.

Abstract: An output circuit for use with an array of high dynamic range analog sensor produces a digital output signal from the array prior to multiplexing, so as to avoid analog multiplexing noise. The analog signals are converted to digital form using a simple, parallel analog-to-digital conversion process at the outputs of low noise array amplifiers. By latching the converted digital output signals into shift registers, the analog multiplex function is obviated and the full dynamic range capability of the detector-amplifier combination is made available.

Abstract: An integrating D-A/A-D converter includes a reference value generation circuit for generating at least one reference value relating to voltage or current, a control circuit for carrying out switching between a digital or analog input and the reference value every predetermined time to connect a switched one to thereby control an integral time, and an integration circuit for respectively integrating an analog value corresponding to the digital or analog input and the reference value switched in sequence every predetermined time and delivered through the control circuit to output an integral value for providing a digital or analog output.

Abstract: An output circuit for use with an array of analog energy detectors includes a system for digital companding which is capable of providing output signals with an enhanced dynamic range. A digital compressor is provided for converting the output signals of the analog detectors into compressed digital values. Accumulators are provided for holding the output signals of the digital compressor. An expander is provided to expand the digital output signals held in the accumulators to determine the energy patterns impinging on the array of analog detectors.

Abstract: A circuit apparatus comprises interface circuitry between analog and digital circuitry. A multiple reference circuit provides a variety of reference voltage signals. The multiple reference circuitry is coupled to a selection circuit that selectively couples one of the reference voltage signals to a first reference input of the interface circuitry and selectively couples another of the reference voltage signals to a second reference input of the interface circuitry, whereby the first and second reference inputs may be selectively coupled to the reference voltages and the circuit maintains a ratiometric relationship between the digital and analog circuitry.

Abstract: A novel serial data communication interface architecture is provided having two modes of operation that are accessed through a chip select signal in combination with a successive approximation registers signal (SARS). Once the internal data conversion begins, the chip select signal may change to any signal state without interrupting the conversion process. Serial interface data output and SARS lines are tri-stated during conversion, while the chip select signal is high. This allows data input, data output, and SARS lines to serve other purposes during conversion. If chip select signal is high at the falling edge of SARS, converted data DO bits are then provided to an internal output register. However, DO data are not immediately routed to the output. Clocking of the output data does not resume until at the first transition to low of chip select signal after the falling edge of SARS.

Abstract: An encoder separates an input digital signal including m bits into the first group and the second group, and encodes each piece of data in the first group to a single code word including n bits in one-to-one correspondence and encodes each piece of data in the second group to two code words each including n bits in one-to-two correspondence. A CDS calculator calculates a CDS value for each of the words output from the encoder. A DSV calculator calculates the accumulated DSV value of the individual words output from the encoder. When the two-n-bit code words are output from the encoder, a code selector selects that one of the code words which decreases the next accumulated DSV value to be calculated by the DSV calculator, according to the CDS value from the CDS calculator and the accumulated DSV value from the DSV calculator.

Abstract: A peak-detection threshold circuit for digitally adjusting an analog peak-threshold level in a magnetic storage read channel. A digital scheme is used to monitor both the positive (PX) and negative (NX) peaks detected in an analog signal. For both positive and negative thresholds T.sub.P and T.sub.N, intermediate peak thresholds T.sub.M are established at selectably lower levels than the peak-detection threshold T.sub.P /T.sub.N. Analog signal peaks are detected when the analog signal crosses the intermediate peak threshold T.sub.M. The corresponding peak-detection threshold T.sub.P /T.sub.N is then compared to the analog peak amplitude. If the intermediate peak threshold T.sub.M and the corresponding peak threshold T.sub.P /T.sub.N are both exceeded by the analog signal, a digital "increment" error flag bit is generated. If only the intermediate peak threshold T.sub.M is exceeded by the analog signal, a digital "decrement" error flag bit is generated.

Abstract: After a windowing operation h(n) performed by space-time weighting of the samples, a method and an apparatus for encoding-decoding a digital signal comprising a sequence of samples x(n) consists in performing a modified discrete cosine transform of the samples to calculate the even order transformation coefficients: ##EQU1## for k .epsilon.[0, . . . , N/2-1] with YN-k=-Yk-1 The coefficient Y2k are expressed in the form of an invertible complex transformation: ##EQU2## for k=0, . . . , N/4-1 with y'n=x2n.h2n y"n xN-2n-1.hN-2N-1W4N=cos(2.pi./4N)+j.sin(2.pi./4N) The invertible comples transformation is calculated using an auxiliary calculation equation: ##EQU3## with: zn=(y2n-yN/2-1-2n)+j(yN-1-2n+yN/2+2n) The invention is applicable to encoding and decoding digital audio or video signals.

Abstract: In a system for compressing, decompressing, and logically manipulating arbitrary bit-maps, the bit-map is aligned along byte boundaries. Each aligned byte is classified as a gap byte if all of the bits of the byte store the same logical value, otherwise the byte is classified as a non-gap byte. Adjacent bytes of the same class are grouped. Groups of gap bytes are encoded into an atomic sequence of bytes as a count of the number of bits included in the grouped gap bytes. Map bytes are duplicated in the atomic sequence and also associated with a count thereof.