Abstract: A sampling frequency converting apparatus includes an input port converting an input image data (X) into a data packet, a data driven engine executing interpolation on the data packet applied from the input port for performing sampling frequency conversion in which an operation is performed in accordance with a predetermined data flow program, an output port outputting the data packet produced by the data driven engine at a second sampling frequency, and an image memory for data processing. The sampling frequency converting apparatus can easily accommodate change of specification of the sampling frequency, and can be easily produced without requiring complicated timing control.

Abstract: A protective device for electric motors for protecting electric motors from high operational temperatures, has an element for determining an operational temperature of an electric motor and an element for automatically switching off of the electric motor when a predetermined limiting operational temperature is exceeded. The determining element is formed as electronic element for determining the operational temperature indirectly from an at least another operational parameter of the electric motor. The element for automatically switching off is formed as electronic element for automatically switching off of the electric motor.

Abstract: A D/A converter divides an input digital data into at least two overlapping digital ranges. The data in the two ranges are converted separately from digital to analog by a low-range and a high-range DAC. The resulting analog signals are then added with a weighting that maintains the proper loudness relationships in the final combined analog output. In a low range of amplitudes, only the low-range DAC performs D/A conversion. Above a predetermined amplitude threshold, some of the high significant bits to the low-range DAC are frozen, while a remaining low significant bits of the low-range DAC are permitted to vary with the input digital data. Above the predetermined amplitude threshold, a digital value is subtracted from the data fed to the high-range DAC. The subtracted value is equal to the frozen value in the low-range DAC. In some embodiments, one or more supplementary bits are developed to smooth the transition between ranges.

Abstract: A multiple slope integrating analog-to-digital converter (ADC) includes many improvements and refinements which eliminate timing and non-linearity errors which accumulate due to a large number of switching operations that occur over an integrate cycle. The ADC includes an integrator and a comparator in which an input voltage to be measured is applied to a summing node at the input of the integrator during an integrate cycle, while at the same time positive and negative reference currents are selectively applied to the summing node by a controller which monitors the output of the comparator in order to limit the voltage magnitude at the output of the integrator. Thereafter, during a de-integrate cycle, the input voltage is disconnected while progressively shallower ramps are measured with a high-speed clock for greater resolution and accuracy. The comparator has a slight hysteresis built in to slightly separate the switching thresholds for positive-going and negative going ramps.

Abstract: An automotive vehicle seat adjusting system according to this invention is constructed to move a seat by a drive circuit. It is also constructed to allow a driver to change, during movement of the seat, the moving speed of the seat as he likes. In the system of this invention, when a signal indicative of the feeling of the driver to the moving speed of the seat is inputted, fuzzy inference is performed in accordance with a speed decision rule to decide an optimal moving speed. The optimal moving speed is decided by a fuzzy inference processor on the basis of the inputted feeling signal and an actual moving speed. The drive circuit is controlled in accordance with the decision at the fuzzy inference processor, whereby the seat is allowed to move at the optimal moving speed.

Abstract: A method and apparatus for calibration of errors in the analog reference voltage input of an analog-to-digital converter. A monolithic reference voltage generator is provided to generate the analog reference which includes a bandgap voltage reference (50) that outputs an untrimmed voltage and a temperature voltage. The untrimmed voltage and temperature voltage are input to a delta-sigma A/D converter (52) which has the output thereof processed through a digital filter (54) to output data on a data bus (58) for storage in an EEPROM (60). The EEPROM (60) is operable in one mode to store temperature history data and, in another mode, to store temperature compensation data. In one mode, temperature compensation parameters are retrieved from the EEPROM (60) and utilized by a multiplier/accumulator circuit (74) to generate compensation factors which are output as a digital word to a DAC (76) for controlling a trim circuit (14).

Abstract: In an A/D converter for electrical signals, the difference, between the instantaneous analog input signal Y(t) and a previous analog signal value Y(t-T), is converted in a fast analog-to-digital converter (3) to a digital sum value. This sum value is added to the preceding digital value, stored in a buffer memory (7, 7'), and the result is fed to a slow but precise D/A converter (2) for generation of the next Y(t-T) value. This has the advantage that good results can be obtained with A/D converters less expensive than those heretofore required to obtain such results.

Abstract: A method for the transferring of 3 phase, asynchronous AC power between a present source supplying power to a load and an alternative source to supply power to the load. The maximum phase displacement is 60 electrical degrees at the load. The transfer can occur between sources which are rotating "forward" or "backward" with respect to each other or jointly with respect to the load. Either present source, alternate source or the load may be used as the timing reference for determining best phase connection of the alternate source to the load.

Abstract: A plug-in timer has a set of input terminals and a set of output terminals as well as a contactor operable to make and/or break electrical connection between these sets of terminals in accordance with a pre-setable 24 hour program. The timer is powered from a small built-in battery, and comprises its own quartz clock and programming-and-control means. The contactor is actuated by a miniature DC motor through a gear and cam arrangement. The operation of the DC motor is controlled by the programming-and-control means, which provides power from the battery to the motor in accordance with a pre-set program; which pre-set program may be modified at any time by way of a keyboard and a numeric display means. The contactor operates by way of hard metal contacts and very little power dissipation occurs within the timer. The timer can be plugged into a special wall switch receptacle and then operates to programmably control the flow of power to the load controlled by this wall switch.

Abstract: A digital-to-analog (D/A) converter used for a digital audio equipment, comprises a binary D/A converting circuit and a calculation processing circuit for receiving an analog signal derived from the binary D/A converting circuit. This D/A converter is capable of considerably reducing a load given to an LPF (low-pass filter) or, of omitting such an LPF. The binary D/A converting circuit outputs an analog signal value corresponding to each sampling point of a digital signal as a first analog output value, and also outputs an analog output signal value delayed by only 1 sampling period as a second analog output value. A difference calculating unit of the calculation processing circuit calculates a difference value between the first analog output value as a first analog input value, and the second analog output value as a second analog input value.

Abstract: A digital-to-analog converter of a current addition type using weighted resistors, includes an input resistor network (4) for providing a resistance dependent on a digital input signal having a predetermined number of bits, and an adder (3) having a first input terminal coupled to the input resistor network and a second input terminal connectable to receive a reference potential, for adding a signal obtained at the first input terminal and the reference potential. The adder also has an output terminal via which a result of an adding operation is output, and the result of the adding operation shows an analog signal corresponding to the digital input signal.

Abstract: A variable length coding apparatus comprises a register for holding a current condition, a ROM for outputting the to-be-transited next state and one data in accordance with a predetermined state transition, a selector for inputting the state corresponding to the information signal value to the register every time the to-be-coded information signal is inputted, and a circuit to feed back the state outputted from the ROM to the register, and the ROM outputs the variable length codes corresponding to the information signal as the above-mentioned data every time the state transits.

Abstract: A circuit and a method for providing an indication of the position of a bit having a selected characteristic in an n-bit binary word are disclosed. The n bits of the binary word are arranged into groups of W bits so that each group is input to a fundamental encoder. The position of the bit having the selected characteristic, among each group of W bits is provided as an encoded output. A multiplexer tree provides a single output indicative of the position of the bit having the selected characteristic in the binary word based on the encoded outputs from the encoders.

Abstract: Method of, and apparatus for, providing automatic detection of potential information loss due to undersampling and automatic detection of potential storage waste due to oversampling based on automatic determination of an analog signal's Nyquist rate. The invention acquires an analog signal, determines a maximum frequency of the analog signal and a corresponding Nyquist rate, and allows a user to select a sampling rate based on either the automatically determined Nyquist sampling rate, a user specified sampling rate, a sampling rate determined by a user specified bandwidth, or a sampling rate determined by user specified available space. The invention also informs a user when a loss of information may occur due to a sampling rate being less than the Nyquist rate. The invention also informs a user when a waste of storage may occur due to a sampling rate being greater than the Nyquist rate.

Abstract: A binary encoding method notably but not exclusively for the encoding of data elements designed to be represented sequentially, according to a preestablished order, for example in counters, inducing a uniform or substantially uniform mean changing rate for each of the binary elements, the data elements being encoded on two distinct fields of binary elements, a reference field and a permutation field, and the sequence of binary elements assigned to the permutation field undergoing a permutation as a function of the value contained in the reference field.

Abstract: A multi-channel analog-to-digital converter includes a counter (20) and a plurality of analog-to-digital conversion cells (10), each of which contain incremental discharge means (11-16) that store a charge proportional to the voltage value of an analog input signal and discharge that charge in increments upon the occurrence of the clock signal, also producing an active signal after the charge has been stored and before the incremental discharge is complete. A register (17) receives a count signal from the counter (20) and stores its value when the active signal goes inactive. A multiplexer (18) selects among the outputs of the plurality of analog-to-digital conversion cells (10) and supplies the selected output as a digital output signal.

Abstract: A data channel is provided that includes a digital decoder that receives a dynamically determined tracking threshold value. The tracking threshold value has a voltage amplitude used by the decoder in decoding a digital voltage signal into binary data. The digital signal is generated using an analog voltage signal that represents data read from a storage medium, such as a magnetic tape or disk. The present method is able to generate appropriate tracking threshold values even during sudden changes in the voltage amplitudes associated with the digital signal. In dynamically determining tracking threshold values, an averaging method with error recovery is employed, that is independent of the particular encoding used with the stored data. For each inputted digital voltage signal that represents a binary bit, a comparison is made between it and a current accepting value. Unless the digital voltage signal is at least equal to the accepting value, it is not used in computing a new tracking threshold value.

Abstract: In a control system for peripheral devices, by operating only one device for digital-to-analogue conversion, the specific output switching corresponding to that specific device for digital-to-analogue conversion is closed and the other output switching corresponding to the other device for digital-to-analogue conversion are open so that the only the output signal of that specific device for digital-to-analogue conversion can be output. Thus, the accuracy of operation of each device for digital-to-analogue conversion can be easily evaluated.

Abstract: A digital-to-analog (D/A) converter characterized by a decoder which decodes a multi-bit digital input into a plurality of cell activation signals; a converter comprising a number of current cells which can be individually activated by respective cell activation signals; a bias generator which develops a bias voltage for the current cells; and a compensator which compensates the bias voltage to reduce the effects of voltage variations in the power supply. The compensator includes a variation detector coupled to the power supply and develops an error signal when the power supply voltage fluctuates. A variation compensator is responsive to the error signal and is operative to stabilize the bias level. The method of the present invention includes the steps of developing a bias voltage from a power supply, sensing voltage variations in the power supply, and compensating the bias voltage to counteract the effects of the voltage variations.

Abstract: When a current that flows into a power output element is greater than a predetermined value, pulse width-modulated signals are formed which vary in inverse proportion to the current value in order to drive the power output element. When an excess current flows into the power output element, therefore, the power output element is allowed to intermittently operate for only short periods of time, and the current can be decreased during the current-limiting operation.