Patents Examined by Shaun M Campbell
  • Patent number: 11152515
    Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 19, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chun-Ya Chiu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Patent number: 11152296
    Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises a substrate having a first surface and a second surface opposite to the first surface, and comprising at least one first recess portion formed in a direction ranging from the first surface toward the second surface, a plurality of first recess conductive patterns formed in the first recess portion, and a first passive element inserted into the first recess portion of the substrate and having a first electrode and a second electrode electrically connected to the plurality of first recess conductive patterns.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: October 19, 2021
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE LTD.
    Inventors: Jae Ung Lee, Yung Woo Lee, EunNaRa Cho, Dong Hyun Bang, Wook Choi, KooWoong Jeong, Byong Jin Kim, Min Chul Shin, Ho Jeong Lim, Ji Hyun Kim, Chang Hun Kim
  • Patent number: 11152431
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory comprises a first variable resistance element coupled between a first wiring and a second wiring, the first variable resistance element including a first variable resistance layer having a first width at a first distance from the first wiring; and a second variable resistance element coupled between the second wiring and a third wiring, the second variable resistance element including a second variable resistance layer having a second width at the first distance from the second wiring. The first width is greater than the second width.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: October 19, 2021
    Assignee: SK hynix Inc.
    Inventors: Young-Seok Ko, Jung-Hun Lee, Hyun-Min Lee, Hyun-Jin Lee
  • Patent number: 11145604
    Abstract: A semiconductor structure, integrated circuit device, and method of forming semiconductor structure are provided. In various embodiments, the semiconductor structure includes a substrate containing a high topography region and a low topography region, an outer protection wall on an outer peripheral portion of the high topography region next to the low topography region, and an anti-reflective coating over the outer protection wall, the high topography region, and the low topography region.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Hsien Ma, Haw-Chuan Wu, Shih-Hao Tsai, Yu-Chuan Lin
  • Patent number: 11145801
    Abstract: Techniques regarding encapsulating one or more superconducting devices of a quantum processor are provided. For example, one or more embodiments described herein can regard a method that can comprise depositing an adhesion layer onto a superconducting resonator and a silicon substrate that are comprised within a quantum processor. The superconducting resonator can be positioned on the silicon substrate. Also, the adhesion layer can comprise a chemical compound having a thiol functional group.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 12, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Richard Alan Haight, Ali Afzali-Ardakani, Vivekananda P. Adiga, Martin O. Sandberg, Hanhee Paik
  • Patent number: 11139343
    Abstract: A display device includes a substrate provided with a first subpixel and a second subpixel; a first electrode provided on the substrate, including a first sub electrode provided on the first subpixel and a second sub electrode provided on the second subpixel; a transparent electrode including a first transparent electrode provided to cover the first sub electrode and a second transparent electrode provided to cover the second sub electrode; an organic light emitting layer including a first organic light emitting layer arranged on the first transparent electrode and a second organic light emitting layer arranged on the second transparent electrode; a second electrode arranged on the organic light emitting layer; a first bank provided between the first transparent electrode and the second transparent electrode to partition the first subpixel and the second subpixel from each other; and a first color filter arranged to correspond to the first subpixel.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: October 5, 2021
    Assignee: LG Display Co., Ltd
    Inventors: Eunil Cho, Howon Choi, YongBaek Lee
  • Patent number: 11133409
    Abstract: A semiconductor device includes a source, a drain, and a channel electrically connected to the source and the drain. The channel has a channel length from the drain to the source which is less than or equal to an electron mean free path of the channel material. A first gate has two arms, each extending between the drain and the source (i.e., at least a portion of the distance between the source and the drain). Each arm of the first gate is disposed proximate to a corresponding first and second edge of the channel. Each arm of the first gate has a periodic profile along an inner boundary, wherein the periodic profiles of each arm are offset from each other such that a distance between the arms is constant. A Bloch voltage applied to the first gate will reduce the effective channel with such that Bloch resonance conditions are met.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 28, 2021
    Assignee: The Research Foundation for The State University of New York
    Inventors: Victor Pogrebnyak, Jonathan Bird
  • Patent number: 11133374
    Abstract: A method includes depositing a magnetic layer over a dielectric layer, and etching a first portion of the magnetic layer, in which a second portion of the magnetic layer that is directly under the first portion of the magnetic layer remains over the dielectric layer after etching the first portion of the magnetic layer. The second portion of the magnetic layer is etched.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: September 28, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Shuo Su, Chun-Tsung Kuo, Jiech-Fun Lu
  • Patent number: 11127808
    Abstract: An active device substrate and a manufacturing method thereof are provided. The active device substrate includes a substrate, first and second scan lines, a data line, first and second active devices and first and second pixel electrodes. The first active device includes a first semiconductor channel layer, a first gate, a first source and a first drain. The first gate is electrically connected to the first scan line. The first pixel electrode is electrically connected to the first drain. The second active device includes a second semiconductor channel layer, a second gate and a second drain. The first semiconductor channel layer is connected to a source region of the second semiconductor channel layer. The first semiconductor channel layer and the second semiconductor channel layer belong to same layer. The second gate is electrically connected to the second scan line. The second pixel electrode is electrically connected to the second drain.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: September 21, 2021
    Assignee: Au Optronics Corporation
    Inventors: Ming-Yao Chen, Kuo-Yu Huang, Wen-Yi Hsu
  • Patent number: 11127889
    Abstract: A method of making a display structure comprises providing a display substrate having a display surface, disposing components on and in contact with the display surface, uniformly blanket coating the display surface with a curable layer of uncured light-absorbing material, and curing the curable layer of uncured light-absorbing material to provide a layer of cured light-absorbing material so that the components project from the layer of cured light-absorbing material without having pattern-wise etched the layer of cured light-absorbing material after the light-absorbing material has been cured. The uniform blanket coating has a thickness greater than a thickness of the component, disposing the components comprises printing the components through the uniform blanket coating such that the components protrude from the uniform blanket coating, or the component is coated with a de-wetting material.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 21, 2021
    Assignee: X Display Company Technology Limited
    Inventors: Glenn Arne Rinne, Christopher Andrew Bower, Matthew Alexander Meitl, Ronald S. Cok
  • Patent number: 11114519
    Abstract: An organic light emitting display device and a method of manufacturing the same are provided that may reduce the resistance of a second electrode and may prevent corrosion and metal migration of a pad electrode without adding a separate mask process, or while reducing the number of mask processes. In the organic light emitting display device, an auxiliary line is connected to a second electrode through an auxiliary electrode, which is provided in the same layer as a first electrode, and a pad cover electrode is configured to cover an upper surface and a side surface of a pad connection electrode so as to prevent the pad connection electrode connected to a pad from being exposed outward.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 7, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Min-Joo Kim, Jung-Sun Beak, Jin-Hee Jang, Nam-Yong Kim
  • Patent number: 11114515
    Abstract: An organic light-emitting diode (OLED) display panel and a manufacturing method thereof are provided. The OLED display panel includes a substrate, a pixel defining layer, an organic light-emitting layer, and an organic encapsulating layer. The pixel defining layer is disposed on the substrate and includes a plurality of recessed regions and a plurality of grooves. The recessed regions communicate with each other through the grooves. The recessed regions and the grooves form a mesh structure. The mesh structure defines a plurality of pixel regions. The organic light-emitting layer is disposed on the pixel defining layer and the organic encapsulating layer is disposed on the organic light-emitting layer.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: September 7, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Bo Yan
  • Patent number: 11107844
    Abstract: A display device can include a first thin film transistor including a first active layer including a first semiconductor material, a first gate electrode overlapping with the first active layer, and a first source electrode and a first drain electrode both electrically connected to the first active layer; a separation insulating layer disposed on the first thin film transistor; and a second thin film transistor disposed on the separation insulating layer and including: a second active layer including a second semiconductor material different from the first semiconductor material, a second gate electrode overlapping with the second active layer, and a second source electrode and a second drain electrode both electrically connected to the second active layer, in which the second active layer of the second thin film transistor has a first thickness and a second thickness greater than the first thickness.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 31, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: SoYeon Je, Hyuk Ji
  • Patent number: 11101235
    Abstract: A semiconductor package includes a build-up structure; a semiconductor disposed on the build-up structure in a flip-chip manner and having a plurality of bumps penetrating therethrough; an electronic element disposed on the semiconductor chip; and an encapsulant formed on the build-up structure and encapsulating the semiconductor chip and the electronic element, thereby improving the product yield and the overall heat dissipating efficiency.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: August 24, 2021
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventor: Lu-Yi Chen
  • Patent number: 11101347
    Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Wei Yu, Tsz-Mei Kwok, Tsung-Hsi Yang, Li-Wei Chou, Ming-Hua Yu
  • Patent number: 11101452
    Abstract: Provided are a packaging device and a display panel packaging method. The device includes: a guide line, a container for containing a package adhesive, a rotary worktable for placing a to-be-packaged device and a winding device for driving the guide line to move. The guide line is mounted on the winding device, and part of the guide line is immerged into the package adhesive so the guide line adhered by the package adhesive passes through the rotary worktable when moving. The to-be-packaged display device is disposed on rotary worktable, thus the guide line contacts with the frit. When the rotary worktable rotates, the guide line moves and passes through the container containing package adhesive. When part of the guide line adhered by package adhesive passes through the rotary worktable, the package adhesive is coated on the frit, thereby achieving uniform coating of the package adhesive under surface tension of frit.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: August 24, 2021
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Zhiliang Jiang, Zhenli Zhou
  • Patent number: 11094622
    Abstract: Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Hsien-Wei Chen
  • Patent number: 11087986
    Abstract: To enhance efficiency of a process of implanting impurities into a silicon carbide semiconductor layer. To provide a method of manufacturing a semiconductor device including a silicon carbide semiconductor layer, the method of manufacturing including: implanting impurities multiple times to an impurity implantation region in the silicon carbide semiconductor layer to different depths, with temperature of the silicon carbide semiconductor layer being set to be equal to or lower than 150° C. In the implanting, impurities may be implanted multiple times to the impurity implantation region to different depths, with temperature of the silicon carbide semiconductor layer being set to be equal to or higher than room temperature.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: August 10, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsushi Nishiyama, Masayuki Miyazaki, Shoji Kitamura
  • Patent number: 11088030
    Abstract: A semiconductor device includes a first gate structure, a second gate structure, a first source/drain structure and a second source/drain structure. The first gate structure includes a first gate electrode and a first cap insulating layer disposed on the first gate electrode. The second gate structure includes a second gate electrode and a first conductive contact layer disposed on the first gate electrode. The first source/drain structure includes a first source/drain conductive layer and a second cap insulating layer disposed over the first source/drain conductive layer. The second source/drain structure includes a second source/drain conductive layer and a second conductive contact layer disposed over the second source/drain conductive layer.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Yao Lai, Ru-Gun Liu, Sai-Hooi Yeong, Yen-Ming Chen, Yung-Sung Yen, Ying-Yan Chen
  • Patent number: 11075361
    Abstract: An organic EL device includes an active region including a plurality of organic EL elements and a peripheral region in a region other than the active region. The organic EL device includes an element substrate including a substrate supporting the organic EL elements; and a thin film encapsulation structure covering the organic EL elements and including a first inorganic barrier layer, an organic barrier layer in contact with a top surface of the first inorganic barrier layer, and a second inorganic barrier layer in contact with the top surface of the first inorganic barrier layer and a top surface of the organic barrier layer. The peripheral region includes a first protruding structure including a portion extending along at least one side of the active region, the first protruding structure supported by the substrate, and an extending portion, of the first inorganic barrier layer, extending onto the first protruding structure.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 27, 2021
    Assignee: Sakai Display Products Corporation
    Inventor: Katsuhiko Kishimoto