Abstract: A semiconductor structure includes a substrate having a doped silicon substrate, a buried oxide layer, and a silicon device layer. A capacitor having an inner electrode and a node dielectric layer is formed in the substrate. The inner electrode and the node dielectric layer extend into the doped silicon substrate. A select transistor is disposed in the silicon device layer. An embedded contact is disposed atop the capacitor to electrically couple a doped region of the select transistor with the inner electrode. A first dielectric layer is disposed around the select transistor. A second dielectric layer is deposited on the first dielectric layer. A contact plug is formed in the second dielectric layer and the first dielectric layer and is in direct contact with the embedded contact. A memory stack with a MTJ element is disposed on the contact plug.

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

Abstract: A semiconductor package including a package substrate including first and second bonding pads, third bonding pads spaced apart from the first bonding pads, and fourth bonding pads spaced apart from the second bonding pads; a first chip stack including first chips stacked on the package substrate, each first chip including first signal pads and first power/ground pads alternately arranged; a second chip stack including second chips stacked on the first chip stack, each second chip including second signal pads and second power/ground pads alternately arranged; first lower wires that connect the first signal pads to the first bonding pads; second lower wires that connect the first power/ground pads to the second bonding pads; first upper wires that connect the second signal pads of the second chips to the third bonding pads; and second upper wires that connect the second power/ground pads of the second chips to the fourth bonding pads.

Abstract: A method for repairing a white defect of a LCD panel includes providing a substrate, the substrate defining pixel areas which themselves comprise a base, a first metal layer, a first insulating layer, a semi-conductor layer, an ohmic contact layer, a source electrode, a drain electrode, and a second insulating layer; forming a through hole by laser in the second insulating layer, the through hole extending through the second insulating layer and separating the drain electrode into two spaced parts; forming a third insulating layer to cover the first conductive layers, the second insulating layer and the though hole and forming a second conductive layer by laser on the third insulating layer to couple the first conductive layer to the second conductive layer.

Abstract: A Pd-coated Cu bonding wire of an embodiment contains Pd of 1.0 to 4.0 mass %, and a S group element of 50 mass ppm or less in total (S of 5.0 to 12.0 mass ppm, Se of 5.0 to 20.0 mass ppm, or Te of 15.0 to 50 mass ppm). At a crystal plane of a cross section of the wire, a <100> orientation ratio is 15% or more, and a <111> orientation ratio is 50% or less. When a free air ball is formed on the wire and a tip portion is analyzed, a Pd-concentrated region is observed on the surface thereof.

Abstract: A display device having an optical panel with improved light extraction efficiency and light conversion efficiency is provided. The display device includes a first substrate, first to third light-emitting elements arranged on the first substrate, an encapsulation layer covering the first to third light-emitting elements, a first light blocking layer arranged on the encapsulation layer, the first light blocking layer including first openings respectively corresponding to the first to third light-emitting elements, a reflective layer arranged on the first light blocking layer, the reflective layer corresponding to an inner surface of each of the first openings, a first color conversion layer, a second color conversion layer, and a light transmission layer respectively located in first openings, a second light blocking layer on the first light blocking layer including second openings overlapping the first openings, and first to third color filter layers located in the second openings.

Abstract: A power semiconductor device includes: a plurality of power modules including control terminals; a heat sink, on which the plurality of power modules are mounted; and a control substrate, to which the control terminals are fixed. The plurality of power modules each include a first protruding portion close to the control terminals, and a second protruding portion far from the control terminals. The heat sink has, at a position corresponding to the first protruding portion, a first recessed portion formed to have an inner diameter larger than an outer diameter of the first protruding portion, and engaged with the first protruding portion. At a position corresponding to the second protruding portion, the heat sink has a second recessed portion formed to have the shape of an elongated hole whose minor diameter is larger than an outer diameter of the second protruding portion, and engaged with the second protruding portion.

Abstract: Embodiments of this disclosure provide a display substrate and a display device. The display substrate includes: sub-pixels located on a base substrate; a first conductive layer located on one side of the base substrate, and including signal lines sequentially disposed in a first direction and extending towards a second direction, and signal line bulges and anode adaptor parts located on the same side of the signal line and disposed alternately; and anodes located between the first conductive layer and a pixel defining layer. Each anode includes an effective part exposed by a corresponding sub-pixel opening, the effective parts of at least part of the sub-pixels have overlapping regions with the signal line bulges and the anode adaptor parts in the second direction, and the second direction is perpendicular to the first direction.

Abstract: An array substrate and a display panel are provided. The array substrate includes a substrate, a gate, a gate insulating layer, an oxide semiconductor layer, and a source-drain metal layer. Material of at least a portion of the gate insulating layer in contact with the oxide semiconductor layer and material of the oxide semiconductor layer include an oxide of the first metal element. Thus, a transition interface between the gate insulating layer and the oxide semiconductor layer has a lower density of defect states, which is beneficial to improve mobility and stability.

Abstract: A display device includes: a substrate; a display element on the substrate; a thin-film encapsulation layer on the display element, the thin-film encapsulation layer including at least one inorganic layer and at least one organic layer; and a lower layer below the thin-film encapsulation layer, the lower layer including a first surface parallel to an upper surface of the substrate and a second surface extending in a direction crossing the upper surface of the substrate. The at least one inorganic layer is has a first thickness on the first surface of the lower layer and a second thickness on the second surface of the lower layer, the first thickness is greater than or equal to the second thickness, and a ratio of the second thickness to the first thickness is about 0.51 or more.

Abstract: A display panel and a display device are provided. The display panel includes: a plurality of first pixel units, a plurality of second pixel units, a plurality of third pixel units and a plurality of first data lines. An effective light-emitting area of the first pixel unit is larger than an effective light-emitting area of the second pixel unit, and larger than an effective light-emitting area of the third pixel unit; orthographic projection of the first data line on the base substrate is not overlapped with an orthographic projection of any one of the first electrode of the first pixel unit, the first electrode of the second pixel unit, and the first electrode of the third pixel unit on the base substrate.

Abstract: A radio frequency (RF) package includes a support having a semiconductor die attach region; a frame that includes an electrically insulative member having a lower side attached to the support and an upper side opposite the support; the frame includes an opening at least partially registered with said semiconductor die attach region; and the frame includes an upper metallization at the upper side of the electrically insulative member and a lower metallization The frame includes first electrically conductive edge connection connecting the first metallization to the first lower metallization.

Abstract: Techniques are disclosed herein for forming a dual flat no-leads semiconductor package. The techniques begin with a package assembly that includes multiple non-singulated packages. The semiconductor package assembly includes a lead frame assembly having dies coupled thereto. A mold encapsulation covers at least portions of the dies and exposes a plurality of leads. A first cutting step exposes sidewalls of leads of the lead frame. An electroplating step deposits a plating on the exposed leads. A second cutting step cuts through the mold encapsulation aligned with the step cut sidewalls. A third cutting step perpendicular to the step cuts and is made through the lead frame and mold encapsulation to singulate the dies into individual packages.

Abstract: A display device includes a substrate, a first electrode disposed on the substrate, a first pixel-defining layer disposed on the first electrode, the first pixel-defining layer having a first opening exposing at least a portion of the first electrode and including a pigment, and a second pixel-defining layer disposed on the first pixel-defining layer and including a dye.

Abstract: The LED structure includes a substrate and a plurality of LED units formed on the substrate. Each LED unit includes a bonding layer formed on the substrate, a first doping type semiconductor layer formed on the bonding layer, a second doping type semiconductor layer formed on the first doping type semiconductor layer, a passivation layer formed on the second doping type semiconductor layer and a portion of the first doping type semiconductor layer; and an electrode layer formed on a portion of the passivation layer and contacting the second doping type semiconductor layer. The plurality of LED units include a first LED unit and a second LED unit adjacent to the first LED unit. The first doping type semiconductor layer of the first LED unit horizontally extends to the first doping type semiconductor layer of the second LED unit adjacent to the first LED unit, and the first LED unit and the second LED unit are individually functionable LED units.

Abstract: Provided is a semiconductor device, including: a semiconductor substrate including a bulk donor; an active portion provided on the semiconductor substrate; and an edge termination structure portion provided between the active portion and an end side of the semiconductor substrate on a upper surface of the semiconductor substrate; wherein the active portion includes hydrogen, and has a first high concentration region with a higher donor concentration than a bulk donor concentration; and the edge termination structure portion, which is provided in a range that is wider than the first high concentration region in a depth direction of the semiconductor substrate, includes hydrogen, and has a second high concentration region with a higher donor concentration than the bulk donor concentration.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Abstract: An organic light-emitting display apparatus includes: a semiconductor layer including a drain region; an interlayer-insulating layer covering the semiconductor layer; a connection metal on the interlayer-insulating layer and contacting the drain region through an interlayer contact hole in the interlayer-insulating layer; a protective insulating layer covering the connection metal; a bridge electrode on the protective insulating layer and contacting the connection metal through a protective contact hole in the protective insulating layer; a planarization layer covering the bridge electrode; and a pixel electrode on the planarization layer and connected to the bridge electrode through a pixel contact hole in the planarization layer. In a plan view, the pixel contact hole is defined outside the protective contact hole.

Abstract: A display apparatus includes a base substrate, a first organic insulating layer disposed on the base substrate, and a second conductive pattern disposed on the first organic insulating layer. The conductive pattern includes a first layer that includes a first metal and that has a first thickness. A diffusion layer that makes contact with the first layer and that includes an oxide of the first metal and has a second thickness less than the first thickness is formed at an uppermost portion of the first organic insulating layer.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.