Patents Examined by Shaun M Campbell
  • Patent number: 12218228
    Abstract: Provided is a semiconductor device, including: a semiconductor substrate including a bulk donor; an active portion provided on the semiconductor substrate; and an edge termination structure portion provided between the active portion and an end side of the semiconductor substrate on a upper surface of the semiconductor substrate; wherein the active portion includes hydrogen, and has a first high concentration region with a higher donor concentration than a bulk donor concentration; and the edge termination structure portion, which is provided in a range that is wider than the first high concentration region in a depth direction of the semiconductor substrate, includes hydrogen, and has a second high concentration region with a higher donor concentration than the bulk donor concentration.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: February 4, 2025
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Koh Yoshikawa, Masayuki Momose, Toshiyuki Matsui
  • Patent number: 12211750
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung-Jung Chang
  • Patent number: 12207500
    Abstract: An organic light-emitting display apparatus includes: a semiconductor layer including a drain region; an interlayer-insulating layer covering the semiconductor layer; a connection metal on the interlayer-insulating layer and contacting the drain region through an interlayer contact hole in the interlayer-insulating layer; a protective insulating layer covering the connection metal; a bridge electrode on the protective insulating layer and contacting the connection metal through a protective contact hole in the protective insulating layer; a planarization layer covering the bridge electrode; and a pixel electrode on the planarization layer and connected to the bridge electrode through a pixel contact hole in the planarization layer. In a plan view, the pixel contact hole is defined outside the protective contact hole.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: January 21, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jiyoon Kim
  • Patent number: 12201032
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 14, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Ying-Cheng Liu, Yi-An Shih, Yi-Hui Lee, Chen-Yi Weng, Chin-Yang Hsieh, I-Ming Tseng, Jing-Yin Jhang, Yu-Ping Wang
  • Patent number: 12200960
    Abstract: A display apparatus includes a base substrate, a first organic insulating layer disposed on the base substrate, and a second conductive pattern disposed on the first organic insulating layer. The conductive pattern includes a first layer that includes a first metal and that has a first thickness. A diffusion layer that makes contact with the first layer and that includes an oxide of the first metal and has a second thickness less than the first thickness is formed at an uppermost portion of the first organic insulating layer.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: January 14, 2025
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Young Ok Park, Byung Hoon Kang, Seung Kim, Su Jin Sung, Gyu In Shim
  • Patent number: 12193265
    Abstract: An organic light-emitting diode (OLED) display panel and an electronic device are disclosed. The OLED display panel includes a display area having a light-emitting area and a non-light emitting area. The OLED display panel includes a cover. The cover includes a base layer, a color resist layer, a black matrix layer, a planarization layer, and a first optical compensation layer. The first optical compensation layer is located corresponding to the black matrix layer.
    Type: Grant
    Filed: September 8, 2020
    Date of Patent: January 7, 2025
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Zhijun Wan
  • Patent number: 12185589
    Abstract: A display device includes a substrate, a first electrode disposed on the substrate, a first pixel-defining layer disposed on the first electrode, the first pixel-defining layer having a first opening exposing at least a portion of the first electrode and including a pigment, and a second pixel-defining layer disposed on the first pixel-defining layer and including a dye.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: December 31, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Pilsoon Hong, Jungi Kim, Junho Sim, Jaehun Lee, Yangho Jung
  • Patent number: 12183572
    Abstract: There is provided a film formation method. The method comprises: preparing a substrate having a first region on which an oxide formed by oxidization of a surface of a conductive material is exposed and a second region on which an insulating material is exposed; replacing a film of the oxide with a film of boron oxide by supplying a boron halide gas to the substrate; etching the boron oxide film in the first region and forming a self-assembled monolayer film in the second region by supplying a gas of a fluorine-containing silane compound to the substrate; and forming a conductive target film selectively in the first region, from the first region and the second region, using the self-assembled monolayer film formed in the second region, the first region having the conductive material exposed thereon.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: December 31, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Yumiko Kawano, Shuji Azumo, Shinichi Ike
  • Patent number: 12183802
    Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region made of a semiconductor material, a first barrier layer is formed on the gate dielectric layer, a second barrier layer is formed on the first barrier layer, a first work function adjustment layer is formed on the second barrier layer, the first work function adjustment layer and the second barrier layer are removed. After the first work function adjustment layer and the second barrier layer are removed, a second work function adjustment layer is formed over the gate dielectric layer, and a metal gate electrode layer is formed over the second work function adjustment layer.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 31, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jing Li, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 12178043
    Abstract: A nonvolatile memory device may include a substrate; a first stacked structure on the substrate; a second stacked structure on the first stacked structure; a channel structure including a first portion passing through the first stacked structure and a second portion passing through the second stacked structure; and a filling structure including a first portion passing through the first stacked structure and extending in a first horizontal direction and a second portion passing through the second stacked structure and extending in the first horizontal direction. The upper end of the first portion of the filling structure may be at a same height as the upper end of the first portion of the channel structure.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 24, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Geunwon Lim
  • Patent number: 12169342
    Abstract: According to one embodiment, a display device includes a first substrate and a second substrate opposed to the first substrate. The first substrate includes an insulating substrate, a switching element located on the insulating substrate and having a relay electrode, an organic insulating film covering the switching element and having a first through-hole penetrating to the relay electrode, a pixel electrode being in contact with the relay electrode via the first through-hole, a first capacitance insulating film covering the pixel electrode, a filler having an insulation property filled in at least the first through-hole and located on the pixel electrode and the first capacitance insulating film, and a common electrode covering the filler.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: December 17, 2024
    Assignee: Japan Display Inc.
    Inventors: Yoshitaka Ozeki, Nobutaka Ozaki
  • Patent number: 12167669
    Abstract: A display device may include a first electrode, a second electrode, an emission layer, an intervening layer, and a first encapsulation layer. The second electrode may overlap the first electrode. The emission layer may be disposed between the first electrode and the second electrode, may overlap the first electrode, and may include a light emitting material. The intervening layer may directly contact the second electrode, may be spaced from each of the first electrode and the emission layer, and may include a fluorine compound. A first section of the first encapsulation layer may overlap the emission layer. The intervening layer may be positioned between the second electrode and a second section of the first encapsulation layer.
    Type: Grant
    Filed: November 24, 2023
    Date of Patent: December 10, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae Sik Kim, Jae Ik Kim, Jung Sun Park, Seung Yong Song, Duck Jung Lee, Yeon Hwa Lee, Joon Gu Lee, Kyu Hwan Hwang
  • Patent number: 12159880
    Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.
    Type: Grant
    Filed: April 19, 2024
    Date of Patent: December 3, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 12154969
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a metal gate stack over the substrate. The metal gate stack has a gate dielectric layer and a work function layer over the gate dielectric layer. The semiconductor device structure also includes a spacer structure over a sidewall of the metal gate stack. A topmost surface of the gate dielectric layer is lower than a topmost surface of the spacer structure. The topmost surface of the gate dielectric layer is closer to the topmost surface of the spacer structure than a topmost surface of the work function layer.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Hao Chang, Li-Te Lin, Pinyen Lin
  • Patent number: 12148694
    Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Cheng-Wei Luo, Kung-Hao Liang
  • Patent number: 12150342
    Abstract: A display device includes a display panel including a main portion, a first bent portion and a second bent portion each extending from the main portion, and a corner portion which connects the first bent portion and the second bent portion to each other and is bendable relative to the main portion. The corner portion which is bendable includes a plurality of protrusion patterns partially disconnected from each other and each bendable relative to the main portion, and each of the plurality of protrusion patterns including a display pixel.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: November 19, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dae Won Choi, Dong Won Kim, Sang Gab Kim, Sang Woo Kim, Gyu Jeong Lee, Sung Won Cho
  • Patent number: 12148761
    Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: November 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki
  • Patent number: 12142715
    Abstract: A light-emitting device includes light-emitting elements connected through a wiring pattern, at least one wire electrically connecting a portion of the wiring pattern to another portion of the wiring pattern, and a reflective member covering a region of the mounting board except for the wiring pattern. The wiring pattern includes wire connection regions at such a distance from each other as to allow the wire to connect the connection regions to each other. The connection regions being used to connect the light-emitting elements in series and/or in parallel by the wire in any one pattern of a plurality of connection patterns with different numbers of series and parallel connections. A plurality of rows of light-emitting elements each constituted of part of the light-emitting elements are disposed on the wiring pattern. The wiring pattern includes an extending portion provided outside of the rows and not provided between the rows.
    Type: Grant
    Filed: August 30, 2020
    Date of Patent: November 12, 2024
    Assignee: NICHIA CORPORATION
    Inventor: Yusuke Kawano
  • Patent number: 12142402
    Abstract: A data storage device includes a substrate including a number of contact pads and a number of passive component packages coupled to the contact pads. The data storage device further includes a memory controller coupled to the substrate, and one or more NAND die stacks coupled to the substrate and in electrical communication with the memory controller. One or more of the passive component packages include a first passive component, a second passive component electrically connected to the first passive component, and a first terminal coupled to the first passive component. The passive component packages further include a second terminal coupled to the second passive component, and a third terminal coupled to a common node of the first passive component and the second passive component.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: November 12, 2024
    Assignee: Sandisk Technologies, Inc.
    Inventors: Ai-Wen Wang, Wei-Chun Shen, Yu-Mei Chen, Guiyang Jiang
  • Patent number: 12144201
    Abstract: A display device includes a display panel including a first region and a second region, and a sensing module on a rear side of the display panel. The first region includes a first pixel area to display an image. The second region includes a second pixel area to display the image and a transmission area to transmit light output by the sensing module. The second region overlaps the sensing module. The second pixel area overlaps a first layer that blocks light output by the sensing module. The transmission area does not overlap the first layer.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: November 12, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jin Woo Park, Won Kyu Kwak, Dong Wook Kim, Hyun-Chol Bang