Abstract: Circuits, methods, and systems for driving a load are described. An exemplary driving circuit may include a plurality of switching devices and a controller electrically connected to the switching devices. The controller may be configured to receive a reference voltage signal indicating a target voltage for the driving circuit to generate to drive the load. The reference voltage signal may correspond to a reference space vector in a reference frame. The controller may also be configured to determine that the reference space vector falls within a holding region in which the reference voltage signal is subject to over-modulation. The controller may then generate an adjusted reference voltage signal by adjusting the reference space vector to match a predetermined space vector associated with the holding region. In addition, the controller may be configured to provide the adjusted reference voltage signal to the plurality of switching devices to drive the load.

Abstract: A switching device having an ultra-fast actuating mechanism for opening electric contacts, the device having a propulsion coil and a conducting disk. A stationary contact collaborates in a closed position with a movable contact, said contacts being moved to an open position by repulsion of the conducting disk. A biasing device generates a closing force to hold the electrical contacts in the closed position. Latching means, for maintaining the movable contact in the open position, includes a magnetic yoke having an attraction coil providing an attraction force of a magnetic movable armature. The movable contact is supported by a contact-bearing support having drive means collaborating with the magnetic movable armature to cause movement thereof when movement of the movable contact takes place.

Abstract: A high security switch for use with an alarm includes a switch assembly for mounting to a fixed structural member. The switch assembly includes a pressure sensitive switch; a magnetic attractive movable body; a cavity having a first end and second end, the cavity confining, directing, limiting and defining the travel of the movable body; and a biasing element near the first end of the cavity to position the moveable body adjacent the first end of the cavity. The switch also includes an actuating element coupled to a movable structural member. In response to moving the actuating element away from the switch assembly the moveable body is magnetically acted upon by the biasing and moved from the second end to the first end of the cavity. The electrical state of the pressure sensitive switch is changed and an alarm activated.

Abstract: The present invention relates to a system and method controlling motor rotation speed and provides a cooling system and method configured to control a temperature associated with an integrated circuit. The cooling system includes a brushless motor, a temperature monitoring input, a clock input, and a motor controller.

Abstract: Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

Abstract: A reconfigurable integrated circuit (“IC”) that has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

Abstract: A plasma source includes a first rod forming a quarterwave antenna, surrounded by at least one parallel rod forming a coupler and which is substantially the same length as the first rod, set to a reference potential, the coupler rods being evenly distributed radially about the first rod, at a distance of around one-fifth to one-twentieth of the quarter of the wavelength.

Abstract: Embodiments of the present disclosure provide input termination circuits that overcome the deficiencies of conventional designs. Specifically, embodiments eliminate large-on chip bypass capacitors that are commonly used for common mode termination, and instead use an active capacitor-multiplier (C-multiplier) circuit at the common mode node. The C-multiplier circuit mimics a large capacitor at high frequency. By eliminating large on-chip bypass capacitors, the IC design (e.g., receiver) is reduced in size, without affecting common mode return loss performance. Embodiments may be used with any applications that require input termination, and particularly with differential applications that require common mode termination.

Abstract: Proposed is a circuit for driving a fluorescent lamp and a light-emitting diode. The circuit may include an inverter; a fluorescent lamp driving branch for driving a fluorescent lamp; a light-emitting diode driving branch for driving a light-emitting diode; a starting branch; and an alternate control branch. By using a simple circuit structure, various embodiments may realize a circuit capable of conveniently and alternately driving a fluorescent lamp and a light-emitting diode.

Abstract: A power control circuit is connected between a power supply voltage and a logic circuit to switch power supplied to the logic circuit. The power control circuit includes a plurality of first power gating cells (PGCs) receiving an external mode change signal in parallel, at least one second PGC connected with one first PGC, at least one third PGC connected with the at least one second PGC, and at least one fourth PGC connected with the at least one third PGC. The second power gating cell, the third PGC, and/or the fourth PGC may include a plurality of gating cells. At least one of the second, third, and fourth pluralities has power gating cells connected in series. Each of the first through fourth PGCs switches power supplied in response to the mode change signal.

Abstract: Piezoelectric vibrating devices have piezoelectric vibrating pieces of which the vibration frequency is measurable individually on a wafer scale, without being affected by adjacent piezoelectric devices on the wafer. An exemplary piezoelectric device includes a piezoelectric vibrating piece having excitation electrodes and respective extraction electrodes. The device includes a package base with two connecting electrodes facing the vibrating piece and connected to respective extraction electrodes. Two pairs of mounting terminals are situated on the outer surface of the package base. Also on the outer surface of the package base are two pairs of opposing castellations that are recessed toward the center of the package base. Edge-surface electrodes connect the first and second main surfaces of the base; one pair is connected to the connecting electrodes and the other pair is connected to respective mounting terminals.

Abstract: The present invention relates to a method for operating a brushless electric motor whose windings are driven by an inverter with the aid of six switches, having an identification unit being provided in order to identify defective switches, a unit for voltage measurement at the outputs of the inverter, and a microcontroller for controlling the switches. Particularly in safety-relevant applications, it is important to quickly determine what characteristic the defective switch has, for example in order to continue to operate the electric motor in an emergency mode, or to switch it off immediately. The defect (F1, F2, F3) is traced and the nature of the defect (F1, F2, F3) in a switch determined by using a different voltage (PWM1, PWM2) to drive those windings (V, W) which are not associated with the defective switch, while a voltage measurement is carried out on the winding (U) associated with the defective switch.

Abstract: An input buffer system with a dual-input buffer switching function includes a first input buffer, a second input buffer, and a multiplexer. The first input buffer is used for outputting a first signal when an input signal is at a logic-high voltage, and the first input buffer is turned off when the input signal is at a logic-low voltage. The second input buffer is used for outputting a second signal when the input signal is at the logic-low voltage. The multiplexer is coupled to the first input buffer and the second input buffer for outputting the first signal or the second signal according to a self refresh signal.

Abstract: A circuit includes E-mode transistors with gate-source junction, a D-mode transistor with gate-source junction. A component generates a voltage drop between the source of the D-mode transistor and the drain of an E mode transistor provided as a signal output. A connection is made between this drain of the E-mode transistor and the gate of the D-mode transistor, and a signal input at the gates of the E-mode transistors.

Abstract: An exclusive-or circuit includes a pass gate controlled by a second input node. The pass gate is connected to pass through a version of a logic state present at a first input node to an output node when so controlled. A transmission gate is controlled by the first input node. The transmission gate is connected to pass through a version of the logic state present at the second input node to the output node when so controlled. Pullup logic is controlled by both the first and second input nodes. The pullup logic is connected to drive the output node low when both the first and second input nodes are high. An exclusive-nor circuit is defined similar to the exclusive-or circuit, except that the pullup logic is replaced by pulldown logic which is connected to drive the output node high when both the first and second input nodes are high.

Abstract: Techniques are provided for transmitting signals through a differential interface between circuits in different power supply domains. A driver circuit in a first power supply domain converts single-ended signals into differential signals. The driver circuit then transmits the differential signals to a receiver circuit in a second power supply domain. The receiver circuit converts the differential signals back into single-ended signals for transmission to circuit elements in the second power supply domain. The differential interface reduces the transmission of noise between circuit elements in the first power supply domain and circuit elements in the second power supply domain.

Abstract: Disclosed are methods and devices, among which is a device that includes a finite state machine lattice. The lattice may include a counter suitable for counting a number of times a programmable element in the lattice detects a condition. The counter may be configured to output in response to counting the condition was detected a certain number of times. For example, the counter may be configured to output in response to determining a condition was detected at least (or no more than) the certain number of times, determining the condition was detected exactly the certain number of times, or determining the condition was detected within a certain range of times. The counter may be coupled to other counters in the device for determining high-count operations and/or certain quantifiers.

Abstract: A time-delayed power switching device for providing power pass-through and timed off conductive pathways to one or more light outputs comprises a power source input, one or more first conductive pathways, one or more second conductive pathways, at least one timing circuit, and at least one relay. The time-delayed power switching device controls power from a power source electrically coupled though the power source input to the timed off conductive pathways by operation of the at least one timing circuit controlling the at least one relay. The relay has a first position adapted to energize the second conductive pathways when receiving a first signal from the timing circuit, and a second position adapted to de-energize the second conductive pathways when receiving a second signal from the timing circuit. Additionally, methods of using one or more time-delayed power switching devices to retrofit lighting areas are disclosed.

Abstract: When a first sub-circuit of a programmable integrated circuit (“IC”) is to be deactivated, a global write enable (GWE) signal is deasserted. In response to deassertion of the GWE signal and a first memory cell associated with the first sub-circuit being in a first state, flip-flops in the first sub-circuit are disabled from changing state. In response to memory cells associated with sub-circuits other than the first sub-circuit being in a second state, flip-flops in the other sub-circuits are enabled to change state. When the first sub-circuit is to be activated, the GWE signal is asserted. Logic implemented by the first sub-circuit is preserved between the deasserting and the asserting of the GWE signal. In response to assertion of the GWE signal and the first memory cell associated with the first sub-circuit being in the first state, flip-flops in the first sub-circuit are enabled to change state.

Abstract: Each of a plurality of inverters includes: a first transistor having one end connected to a first terminal; and a second transistor having one end connected to a second terminal and the other end connected to the other end of the first transistor. The first transistors included in the inverters located at either odd-number orders or even-number orders counted from an input terminal side of an inverter chain circuit become conductive when a pre-charge signal has a first state to pre-charge the other end of the first transistors, and become non-conductive when the pre-charge signal has a second state.