Abstract: A method for debugging a processor which is executing vertices of a software application is described. Each vertex is assigned to a programming thread of the processor. The processor has debug hardware for raising exceptions in certain break conditions. The method comprises inspecting a vertex identifier, comparing the vertex identifier and raising an instruction exception event for the programming thread if the vertex identifier assigned to the thread matches the vertex break identifier in the debug hardware. Exceptions are raised based on identified vertices, rather than just individual instructions or instruction addresses.

Abstract: Methods, systems, and devices for enabling transitions between half-duplex and full-duplex modes in wireless communications are described. A user equipment (UE) may transmit to a base station a first indication of a switching latency for transitioning between a half-duplex mode and a full-duplex mode. The UE may receive, from the base station in accordance with the first indication of the switching latency, a second indication that the UE is to transition to one of the half-duplex mode or the full-duplex mode. The UE may transition to the half-duplex mode or the full-duplex mode based on receiving the second indication.

Abstract: Systems, apparatuses and methods suitable for optimizing synchronization mechanisms for multi-core processors are provided. The synchronizing mechanisms may be optimized by receiving a command stream which comprises a plurality of commands including one or more wait commands, wherein each wait command has an associated state and one or more associated conditions; sequentially processing each command in the command stream until a wait command is reached; checking the state associated with the wait command to be processed, wherein if said state is a blocking state, further processing of commands in the command stream is paused until each of said wait command's associated conditions are met, and wherein if said state is a non-blocking state, the next command in the command stream is retrieved and processed.

Abstract: There is provided determination of a beam configuration between a first radio transceiver device and a second radio transceiver device. The first radio transceiver device performs beam searching by transmitting a first sounding signal in all transmit beam configurations in a set of transmit beam configurations; and receiving, from the second radio transceiver device, a second sounding signal in all receive beam configurations in a set of receive beam configurations. The first radio transceiver device determines a beam configuration based on the receive beam configuration in the set of receive beam configurations in which the second sounding signal having best predetermined metric was received.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller and the memory device communicate using a plurality of flash channels, where each channel is mapped to one or more dies of the memory device. Each of the one or more dies of the memory device are associated with one or more strobes of a strobe cycle of a respective flash channel, where a die is provided power during a respective strobe. The controller is configured to, using a time division peak power management (TD-PPM) operation, change an association of a strobe from a first channel to a strobe of a second channel, which may adjust an amount of power provided to each of the channels and improve performance and latency of the data storage device.

Abstract: Methods, systems, and devices for read operations for regions of a memory device are described. In some examples, a memory device may include a first cache for storing mappings between logical addresses and physical addresses of the memory device, and a second cache for storing indices associated with entries removed from the first cache. The memory device may include a controller configured to load mappings to the first cache upon receiving read commands. When the first cache is full, and when the memory device receives a read command, the controller may remove an entry from the first cache and may store an index associated with the removed entry to the second cache. The controller may then transmit a mapping associated with the index to a host device for use in a HPB operation.

Abstract: A covering includes an outer material, a plurality of conductive-fibers, and a fastening material. The outer material includes a front surface and a back surface and the conductive-fibers are disposed between the front surface and the back surface. The conductive-fibers are configured to receive a voltage that causes the conductive-fibers to repel and remove dust from the front surface of the outer material. The fastening material is coupled to the back surface of the outer material and facilitates releasably attaching the outer material to an article.

Abstract: Some embodiments provide a method for a neural network inference circuit that executes a neural network. The method loads a first set of inputs into an input buffer and computes a first dot product between the first set of inputs and a set of weights. The method shifts the first set of inputs in the buffer while loading a second set of inputs into the buffer such that a first subset of the first set of inputs is removed from the buffer, a second subset of the first set of inputs is moved to new locations in the buffer, and a second set of inputs are loaded into locations in the buffer vacated by the shifting. The method computes a second dot product between (i) the second set of inputs and the second subset of the first set of inputs and (ii) the set of weights.

Abstract: The data duplication system comprises a first storage device having a first data protection area for storing backup images of multiple generations of a first volume for data read/write by an external device. The first data protection area is inaccessible to the external device. A second storage device coupled to the first storage device. The first storage device creates a second volume for storing a backup image of a particular generation of the plurality of generations of backup images stored in the first data protection area. The second storage device creates a third volume for storing the copy data, and a virtual volume that is mapped to the second volume of the first storage device. The second storage stores the backup data of a specific generation stored in the second volume in the third volume via the virtual volume by forming a pair that copies the data in the virtual volume and the third volume.

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to a direct memory access controller. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the direct memory access controller may concurrently load next input into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

Abstract: A method of performing instructions in a computer processor architecture includes determining that a load instruction is being dispatched. Destination related data of the load instruction is written into a mapper of the architecture. A determination that a compare immediate instruction is being dispatched is made. A determination that a branch conditional instruction is being dispatched is made. The branch conditional instruction is configured to wait until the load instruction produces a result before the branch conditional instruction issues and executes. The branch conditional instruction skips waiting for a finish of the compare immediate instruction.

Abstract: The present invention relates to a cap for covering an opening of a container, preferably the opening of a bottle. The present invention is characterized by a cork body having a cylindrical configuration and configured in two portions between which there is arranged an impermeable sheet element according to the longitudinal direction. The presence of an impermeable sheet allows using a conventional closure material preventing permeability in the longitudinal direction both to prevent the liquid from coming out of the container and to prevent bacteria or contaminants from the outside from entering.

Abstract: The described embodiments set forth techniques for providing a backup progress estimate for a backup of a source file system volume (FSV). The techniques involve determining, for the source FSV, a backup size during performance of backup operations. The operations can include determining the backup size based on a number of files on the source FSV. Additionally, the operations can include copying files of the source FSV and/or propagating corresponding files of a destination FSV to a location of the backup of the source FSV on a destination storage device and updating one or more metrics using a number of files and/or a number of bytes copied and/or propagated to the backup. In this manner, a progress indication for the backup may be determined based on the one or more metrics responsive to files and/or directories of the source file system volume being stored on a destination storage device.

Abstract: A pressurized gas accumulator has a hollow body which extends along a longitudinal axis and at least one connection piece. The hollow body has at least one layer of a weave structure with a plurality of warp threads running next to one another and a weft thread woven with the warp threads and oriented perpendicular thereto. The warp threads are oriented essentially parallel or essentially perpendicular to the longitudinal axis of the hollow body. A method for producing a pressurised gas accumulator and to a device for carrying out said method is also provided.