Abstract: The present disclosure relates generally to computer systems and, more particularly, to a cache refresh system and related processes and methods of use. The method of refreshing data in cache memory includes: setting, by a computer system, a refresh indicator to “true”; refreshing data in the cache memory, by the computer system, upon a determination that the refresh indicator is set to “true”; and setting, by the computer system, the refresh indicator to “false” after the refreshing of the cache memory.
Abstract: A wireless client device communicates, to an access point over a secure channel, a mapping of a dynamic device address to a stable device address. By communicating the mapping, the access point is able to determine that packets received from two different device addresses originate from a common device. The access point is then able to maintain an association between the originating device and other network resources assigned or allocated to the originating device, such as IP addresses or infrastructure station address, which is used to identify the originating device to other devices outside the network in some embodiments.
Abstract: Apparatuses and associated methods of manufacturing are described that provide for cut-resistant yarn structures. An example cut-resistant yarn structure includes a first cut-resistant core filament a second cut-resistant core filament. The yarn structure further includes a first covering yarn that is wound over the first cut-resistant core filament and the second cut-resistant core filament. The first covering yarn includes a core-spun yarn in which staple fibers are spun over a third cut-resistant core filament. The yarn structure also includes one or more covering layers wound over the first covering yarn that may serve as the exterior layer for the cut-resistant yarn structure. In some instances, the first and second cut-resistant core filaments include a core-spun yarn in which staple fibers are spun over the first cut-resistant core filament and/or the second cut-resistant core filament.
Abstract: Systems, apparatuses, and methods for managing a number of wavefronts permitted to concurrently execute in a processing system. An apparatus includes a register file with a plurality of registers and a plurality of compute units configured to execute wavefronts. A control unit of the apparatus is configured to allow a first number of wavefronts to execute concurrently on the plurality of compute units. The control unit is configured to allow no more than a second number of wavefronts to execute concurrently on the plurality of compute units, wherein the second number is less than the first number, in response to detection that thrashing of the register file is above a threshold. The control unit is configured to detect said thrashing based at least in part on a number of registers in use by executing wavefronts that spill to memory.
Type:
Grant
Filed:
December 29, 2020
Date of Patent:
January 16, 2024
Assignee:
Advanced Micro Devices, Inc.
Inventors:
Bradford Michael Beckmann, Steven Tony Tye, Brian L. Sumner, Nicolai Hähnle
Abstract: Techniques for providing horizontally scaled caching of versioned data are provided. In some aspects, the techniques described herein relate to a method including initializing a first version cache (VC) object based on a version of data stored in a data storage device; replicating the first VC to generate a second VC; receiving a write operation at the first VC; generating a delta for the write operation, the delta representing a change in the version of data; writing the delta to a persistent replication log, the persistent replication log storing an ordered set of deltas including the delta; writing data in the write operation to the data storage device; and applying the ordered set of deltas at the second VC to update data stored by the second VC.
Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.
Abstract: Hinged closures for containers are provided. The hinged closures allow for a closure that can be held in the open position with a large opening angle. The hinged closures include a lid portion and a tamper evident band interconnected by a hinge portion. The hinge portion can be formed from two connecting bands and a central flexible band, or a continuous band having variable thickness and a central thinner flexible area.
Abstract: Provided in the present disclosure are a downlink control channel receiving and transmitting method and device. The method includes: determining a target receiving manner to be used for receiving a downlink control channel; and receiving, according to the target receiving manner, the downlink control channel sent by a base station. The present disclosure enables a terminal to receive a downlink control channel according to a target receiving manner, thus improving performance of a 5G system.
Type:
Grant
Filed:
May 31, 2022
Date of Patent:
January 9, 2024
Assignee:
Beijing Xiaomi Mobile Software Co., Ltd.
Abstract: Methods, systems, and devices for power control for boot-up of memory systems are described. A memory system may be configured to boot-up using two different power modes: a lower-power mode, and a higher-power mode. The memory system may perform a series of evaluations to determine whether the memory system is to switch to the lower-power mode during boot-up operations, or stay in the higher-power mode. For example, the memory system may check one or more of: a history of previous boot-up failures, a voltage of an associated power management integrated circuit, a history of asynchronous power loss at the device, a power-mode configuration of the host device, or a history of host-initiated power-down commands. In some examples, by switching to the lower-power mode, the memory system may avoid repeatedly failing multiple boot-up cycles and may instead successfully boot-up the memory system.
Abstract: A child safety lid is provided and used to close the opening of content containers including rigid and flexible containers/bags. The cover requires a multiple step process in order to be removed and helps to prevent inadvertent or accidental openings of the container. The lid/cover can comprise a top member, a locking member, a bottom member and a seal member. The top member can be secured to the bottom member with the locking member captured therebetween and the seal member can extend downward from the bottom member and contact an internal shelf/ledge disposed within the container near the container opening. In one embodiment, the seal member and bottom member can be bonded to each other through an overmolding process. In one embodiment, the seal can be constructed from an elastomer material.
Type:
Grant
Filed:
March 24, 2022
Date of Patent:
January 9, 2024
Assignee:
BURST OUT INNOVATIONS, INC.
Inventors:
Gary K Goldfarb, Werner Blumenthal, Alexander Zuleta, Dwight D Brooks