Patents Examined by Sheila V. Clark
  • Patent number: 10347549
    Abstract: A power semiconductor device module includes a metal baseplate and a plastic housing that together form a tray. Power electronics are disposed in the tray. A plastic cap covers the tray. Electrical press-fit terminals are disposed along the periphery of the tray. Each electrical terminal has a press-fit pin portion that sticks up through a hole in the cap. In addition, the module includes four mechanical corner press-fit anchors disposed outside the tray. One end of each anchor is embedded into the housing. The other end is an upwardly extending press-fit pin portion. The module is manufactured and sold with the press-fit pin portions of the electrical terminals and the mechanical corner anchors unattached to any printed circuit board (PCB). The mechanical anchors help to secure the module to a printed circuit board. Due to the anchors, screws or bolts are not needed to hold the module to the PCB.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: July 9, 2019
    Assignee: LITTELFUSE, INC.
    Inventor: Thomas Spann
  • Patent number: 10297533
    Abstract: A semiconductor device is provided, including: a bottom portion having a pad formed of a conductive material; a lid portion covering at least a part of the bottom portion; and a first terminal portion and a second terminal portion which are provided in parallel with each other, are fixed to the lid portion, and each contact a corresponding pad, wherein: the first terminal portion is provided with a first plate-shaped portion; the second terminal portion is provided with a second plate-shaped portion; and each of the first plate-shaped portion and the second plate-shaped portion has a principal surface in a direction facing the pad and is flexible in a direction toward the pad.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yoshihiro Kodaira
  • Patent number: 10297467
    Abstract: Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: May 21, 2019
    Assignee: Intel Corporation
    Inventors: Charles H. Wallace, Paul A. Nyhus
  • Patent number: 10297534
    Abstract: A single chip integrated circuit (IC) package includes a die pad, and a spacer ring on the die pad defining a solder receiving area. A solder body is on the die pad within the solder receiving area. An IC die is on the spacer ring and is secured to the die pad by the solder body within the solder receiving area. Encapsulating material surrounds the die pad, spacer ring, and IC die. For a multi-chip IC package, a dam structure is on the die pad and defines multiple solder receiving areas. A respective solder body is on the die pad within a respective solder receiving area. An IC die is within each respective solder receiving area and is held in place by a corresponding solder body. Encapsulating material surrounds the die pad, dam structure, and plurality of IC die.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: May 21, 2019
    Inventor: Wing Shenq Wong
  • Patent number: 10256198
    Abstract: Techniques for reducing warpage for microelectronic packages are provided. A warpage control layer or stiffener can be attached to a bottom surface of a substrate or layer that is used to attach the microelectronics package to a motherboard. The warpage control layer can have a thickness approximately equal to a thickness of a die of the microelectronics package. A coefficient of thermal expansion of the warpage control layer can be selected to approximately match a CTE of the die. The warpage control layer can be formed from an insulating material or a metallic material. The warpage control layer can comprise multiple materials and can include copper pillar segments to adjust the effective CTE of the warpage control layer. The warpage control layer can be positioned between the microelectronics package and the motherboard, thereby providing warpage control without contributing to the z-height of the microelectronics package.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 9, 2019
    Inventors: Eric J. Li, Guotao Wang, Huiyang Fei, Sairam Agraharam, Omkar G. Karhade, Nitin A. Deshpande
  • Patent number: 10249579
    Abstract: An electronic apparatus includes, a substrate, one or more routing layers, and an active shield layer. The substrate includes active devices. The routing layers are electrically connected to the active devices and are configured to route electrical signals to and from the active devices. The active shield layer is disposed within a routing layer nearest to the substrate, the active shield layer includes metallic traces configured conduct active-shield signals that provide an indication of an attack on the apparatus.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 2, 2019
    Inventors: Yuval Kirschner, Arnon Sharlin
  • Patent number: 10236227
    Abstract: An electronic package is provided, including a circuit portion, an electronic element disposed on the circuit portion and a lid member disposed on the circuit portion to cover the electronic element. A separation portion is formed between the lid member and the electronic element. The lid member facilitates to prevent warping of the overall package structure. The invention further provides a method for fabricating the electronic package.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: March 19, 2019
    Assignee: Siliconware Prescision Industries Co., Ltd.
    Inventors: Lung-Shan Chuang, Ching-Wen Chiang, Tzung-Yen Wu, Chun-Hung Lu
  • Patent number: 10217873
    Abstract: A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 26, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Heap Hoe Kuan
  • Patent number: 10141254
    Abstract: A direct bonded copper (DBC) power module with elevated common source inductance is adapted for use as a half bridge in an electric drive for an electric vehicle. Etching patterns on the DBC substrates provide indented notches for concentrating magnetic flux in the power loops. Etched gate traces form gate loops with coil windings disposed within or overlapping the notches in order to enhanced the common source inductance for each switching transistor (such as an IGBT). Switching loss is reduced and fuel economy is improved for the electric vehicle with minimal impact on packaging size and at no additional cost.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: November 27, 2018
    Inventors: Zhuxian Xu, Chingchi Chen
  • Patent number: 10056339
    Abstract: A semiconductor device includes a substrate, a first insulation layer, data storage elements, a contact plug, and a first dummy dam. The first insulation layer is on the substrate and includes a pad region and a peripheral region adjacent to the pad region. The data storage elements are on the pad region of the first insulation layer. The contact plug penetrates the first insulation layer on the peripheral region. The first dummy dam penetrates the first insulation layer and is disposed between the data storage elements and the contact plug.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: August 21, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeon-Woo Jang, Junghwan Park, Ramakanth Kappaganthu, Sungjin Kim, Junyong Noh, Jung-Hoon Han, Seung Soo Kim, Sungjin Kim, Sojung Lee
  • Patent number: 10051735
    Abstract: A product and method for packaging high power integrated circuits or infrared emitter arrays for operation through a wide range of temperatures, including cryogenic operation. The present invention addresses key limitations with the prior art, by providing temperature control through direct thermal conduction or active fluid flow and avoiding thermally induced stress on the integrated circuits or emitter arrays. The present invention allows for scaling of emitter arrays up to extremely large formats, which is not viable under the prior art. The present invention eliminates or otherwise reduces risks associated with vaporization of coolant within the heatsink structure.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 14, 2018
    Assignee: Oleson Convergent Solutions LLC
    Inventor: Jim Oleson
  • Patent number: 9812416
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer and a second dielectric layer. The metal trace is connected to a ball connection by a first via in the first dielectric layer and second via in the second dielectric layer. The metal trace is connected to a test pad at a connection point, where the connection point is under the first dielectric layer. The metal trace under at least the first dielectric layer and the second dielectric layer has increased stability and decreased susceptibility to cracking in least one of the ball connection, the connection point, the first via or the second via as compared to a metal trace that is not under at least a first dielectric layer and a second dielectric layer.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jiun Yi Wu, Hsueh-Lung Cheng, Shou-Yi Wang
  • Patent number: 9773685
    Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact or near proximity of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: September 26, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Rajendra D. Pendse, KyungOe Kim, TaeWoo Kang
  • Patent number: 9768134
    Abstract: A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: September 19, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Anilkumar Chandolu, Kenneth N. Hagen
  • Patent number: 9761490
    Abstract: A method for forming a semiconductor device includes forming a device structure having a floating gate, control gate, sidewall spacers, and source and drain regions. The device structure includes contact-hole regions and non-contact-hole regions. The method also includes forming a photo resist layer overlying the contact hole regions in the device structure and exposing the non-contact-hole regions, and forming a protective layer overlying the sacrificial layer and the exposed non-contact-hole regions. Next, an interlayer dielectric layer overlying the protective layer, and CMP (chemical mechanical polishing) is used to remove the inter-layer dielectric layer and the protective layer from above the photo resist. The photo resist layer is then removed from the contact-hole regions to expose contact holes.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yun Yang
  • Patent number: 9741690
    Abstract: An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 9721852
    Abstract: A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (TSV) layer including a first logic die and TSVs. The logic circuit-TSV layer is within the overmold layer, and the TSVs are electrically exposed at a top surface of the overmold layer. The first package may be fabricated and tested by a first party prior to being provided to a second party. A second package includes a second logic die. The second party may attach the second package to the first package at the electrically exposed TSVs of the first package to realize a complete and functional semiconductor device.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Richard Stephen Graf, David Justin West
  • Patent number: 9627345
    Abstract: A semiconductor-mounted product includes a semiconductor package, a circuit board, a solder bonding part, and a resin reinforcing part. Wiring is formed on the surface of the circuit board, and the semiconductor package is mounted on the circuit board. The solder bonding part electrically connects the semiconductor package with the wiring. The resin reinforcing part is formed on a side surface of the solder bonding part such that the solder bonding part is partially exposed. The bonding part has a first solder region formed closer to the semiconductor package than the circuit board, and a second solder region formed closer to the circuit board than the semiconductor package.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: April 18, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Atsushi Yamaguchi, Yasuo Fukuhara
  • Patent number: 9627327
    Abstract: Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 18, 2017
    Inventors: Baik-woo Lee, Dong-hun Lee, Jae-gwon Jang, Chul-yong Jang
  • Patent number: 9620388
    Abstract: A method of making an integrated circuit package. A leadframe having a die attach paddle surrounded by lead portions is formed. Middle channels underlying in said die attach paddle portion in a region thereof adapted to receive a first die are formed.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 11, 2017
    Inventors: You Chye How, Maria Christina Bernardo Violante