Abstract: A ring oscillator consisting of a plurality of series connected amplifier stages alternatingly energized by first and second voltages negatively correlated to each other. The output of the final amplifier stage is inverted and connected to the input of the first stage. The second voltage is derived from the first voltage by way of an inverting amplifier which is dimensioned to render the total sensitivity K=df/dVDD zero.

Abstract: An integrated circuit includes an oscillator circuit for generating an output signal having a desired frequency. The oscillator circuit includes a capacitive device having a controllable capacitance value responsive to a control signal. A control circuit is connected to the oscillator circuit for controlling the capacitance value so that the oscillator circuit generates the output signal at the desired frequency. The control circuit includes a memory for storing a digital control word and a control signal generating circuit for converting the digital control word into the control signal for the capacitive device. Setting the desired frequency of the output signal is performed internal to the integrated circuit without requiring complex control circuitry for switching among various capacitors.

Abstract: A digital temperature compensating crystal oscillator, and a method for stabilizing the frequency thereof, in which not only the vibration phenomenon caused during the conversion of analog signals to digital signals in spite of a constant ambient temperature is decreased, but also the output frequency vibrations caused by the noises of analog devices are also decreased, thereby improving the stability and the reliability. If an output temperature data of an analog/digital converter is a first sampling data, then the output temperature data of the analog/digital converter is used directly as a temperature code for obtaining a temperature compensating data, to be stored into a memory. If it is not a first sampling data, then the output temperature data of the analog/digital converter are accumulated up to a predetermined number of times, and an average of accumulated values is supplied into the memory as a temperature code for obtaining the temperature compensating data.

Abstract: A cost-effective continuous phase logic-based modulator and demodulator are provided to allow communications using binary frequency shift keying (BFSK) as well as M-ary FSK techniques. The modulator of the 1-bit precision modem architecture is based on a 1-bit precision numerically controlled oscillator (NCO), which provides complete programmability with respect to a frequency of the 1-bit precision logic-based modulator and/or demodulator. The 1-bit precision NCO includes an adder and a phase accumulator register which is clocked by a master clock signal. A two-input multiplexer has a single bit symbol value to generate BFSK, or larger input multiplexers can be implemented to provide M-ary FSK. The output of the 1-bit precision NCO is upconverted to an intermediate frequency using a simple logic function, i.e., XNOR logic. Alternatively, the intermediate frequency may be arrived at without the need for upconversion by directly utilizing a harmonic alias at a desired IF frequency.

Abstract: A phase compensation apparatus and method for a digital modulator which is suitable for maintaining the optimum operating state of the modulator provided in a digital television repeater by reducing the phase distortion produced from the modulator.

Abstract: A demodulator circuit for demodulating a frequency modulated input, which includes a detector (14) that is operable to produce a demodulated signal from an incoming frequency modulated signal. A tuning circuit (19) is connected to the detector and operable to vary the frequency response characteristics of the detector. An auxiliary detector (25, 26) is connected to receive a reference frequency signal and to provide an auxiliary tuning signal to the detector on the basis of detection of the reference frequency signal.

Abstract: A variable-tuned type YIG oscillator accompanied with substantially no mechanical variations in the resonance circuit and a method of manufacturing the same are provided. An amplifier element, electrode, circuit pattern and others of the oscillator circuit portion of a YIG oscillator are integrated on the front face of a semiconductor substrate by the monolithic microwave integrated circuit manufacturing technique. A coupling loop is formed as a thick film conductor shaped so as to surround at least a portion of the outer periphery of a YIG crystal ball on the semiconductor substrate having the amplifier element, electrode, circuit pattern and others formed thereon. A hole for positioning a YIG crystal ball at a predetermined position inside of the coupling loop is formed in the semiconductor substrate from the front surface of the substrate, and the YIG crystal ball is fitted and fixed in the hole.

Abstract: A phase locked loop circuit includes an input comparator (2) capable of generating a deviation signal which can be used for driving an oscillator (5) so as to generate an output signal (CLKOUT) locked to the input signal. The oscillator (5) can operate according to a plurality of characteristics under the control of a control circuit (8) including searching circuits arranged to carry out a first search phase by scanning the family of characteristics admitted for the operation of the oscillator (5) by bands of progressively reduced width, according to a general, dichotomic procedure. Upon completion of this first search phase, additional circuits of fine search are destined to identify the optimum operating point, compensating possible fluctuations of the characteristics.

Abstract: A ring oscillator includes a coarse delay control block including a plurality of coarse delay gates, and a fine delay control block including a plurality of fine delay gates. The total delay of the fine delay control block is larger than a single delay step of the coarse delay control block, whereby variations of the delay step do not cause an adverse effect on the jitter characteristic of a PLL circuit having the ring oscillator. In a normal operation, the coarse delay control block increments the delay step after the total of the delay steps of the fine delay control block exceeds the delay step of the coarse delay control block.

Abstract: Methods and systems are disclosed for eliminating a phase transient of a controlled frequency oscillator caused by replacing a first reference signal by a second reference signal when the first reference signal becomes corrupted or otherwise unavailable, and for running a controlled frequency oscillator in a frequency-controlled holdover mode. The contradictory requirements of using a relatively low-cost controlled frequency oscillator tunable over a relatively wide frequency range and achieving high stability of its frequency in holdover mode are satisfied.

Abstract: A demodulator circuit for demodulating a signal ASK-modulated with modulation pulses equal in duration, and having a small depth of modulation and large dynamic range comprises an amplitude limiter (10) through which an amplitude-dependent current flows when the amplitude of the signal to be demodulated exceeds its limiting threshold value. Furthermore comprised is an envelope detector (12) to the input of which the signal to be demodulated is applied, as well as a differentiating network (14) configured so that it differentiates the output signal of the envelope detector (12) and outputs a signal pulse only when the change in amplitude of this output signal is in one direction. A bandpass filter (18) in the demodulator circuit passes, from a signal derived from an amplitude-dependent current from the amplitude limiter (10), the frequency component attributed to the duration of the modulation pulses.

Abstract: A modulated signal is translated to a broadcast frequency by a translation phase lock loop. In the translation phase lock loop the output frequency, which is the broadcast frequency, is mixed with a translation frequency, and the resulting translated frequency is compared to the modulated signal. If an amplitude modulator is inserted into the translation loop, the phase comparison/feedback nature of the phase lock loop will tend to cancel the phase noise introduced in the amplitude modulation process. Any other circuits placed within the loop will tend to have any phase noise they introduce, which is in the phase lock loop bandwidth, canceled by the loop.

Abstract: A PLL circuit used in an apparat as for reading and writing data to a disk compensates for noise which causes a false clock signal or for missing clock signals which can be caused by a scratch or smudge on the surface of the disc. The PLL circuit includes a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal and generates a phase difference signal. A charge pump receives the phase difference signal and generates an output signal, which is filtered by a low pass filter. The filtered signal is provided to a voltage controlled oscillator, which generates an oscillation output signal. A divider divides the oscillation output signal and generates the feedback signal. A time information generating circuit generates time information of the oscillation output signal, indicating the time period where it is presumed the reference signal is or should be received.

Abstract: This device includes a frequency synthesizer (12) comprising two phase-locked loops (L1 and L2). The one comprises a low-pass filter (68) and the other a high-pass filter (49). The loop with the low-pass filter fixes the basic frequency of the synthesizer and the other corrects the phase noise. With this arrangement it is easy to apply a modulation frequency to the terminal (11) that is not disturbed by said loops if this modulation frequency is found to be higher than the cut-off frequency of the low-pass filter.

Abstract: An absolute phasing circuit having a simplified phase rotating means constituting a remapper. The phase rotation angle of a receiving phase for the signal point arrangement on the transmitting side is detected, and a phase rotation signal RT (3) based on the detected phase rotation angle is outputted from a frame synchronization circuit (2). Phases of baseband demodulated signals I and Q through a demodulator circuit (1) are rotated by 45° through a ROM (3) constituting the remapper. A logic conversion circuit (4), receiving the baseband demodulated signals I and Q through the demodulator circuit (1) and phase rotated baseband demodulated signals i and q from the ROM (3), performs inversion of code and exchange of the baseband demodulated signals selectively and delivers a baseband demodulated signal matched with the signal point arrangement on the transmitting side.

Abstract: A phase lock loop (PLL) circuit has an oscillation circuit operating in synchronism with a horizontal synchronizing signal. The PLL circuit also has a DC level decision circuit for deciding the DC level of a vertical synchronizing signal during a return period, and a logic circuit for automatically selecting the oscillation circuit according to the DC level decided in the DC level decision unit. Thus, even if there is an increase in the oscillation characteristics, this PLL circuit can automatically select the necessary oscillation characteristics without a need for expanding an operation frequency of a voltage controlled oscillation circuit.

Abstract: An oscillator structure includes at least one oscillator circuit and at least one resonator. The oscillator circuit is disposed on a support and the resonator is situated essentially within the support and/or is a constituent part of the support. The resonator is preferably formed by an electrical conductor and the oscillator circuit is preferably formed by an integrated electronic circuit.

Abstract: A method of controlling a frequency synthesizer and a frequency synthesizer having a controllable output signal frequency and including a direct digital synthesizer whose output signal is coupled to the input of a phase-locked loop. To reduce the settling time of the synthesizer, the direct digital synthesizer includes a control circuit for controlling the frequency of the direct digital synthesizer from a first frequency to a second frequency in accordance with predetermined frequency steps.

Abstract: A voltage controlled oscillator has first and second complementary output terminals. A first edge delay circuit has an input terminal, an output terminal, and a control input terminal. The input terminal is coupled to the first complementary output terminal. A first comparator has a first, second and third input terminal, an output terminal, and a control input terminal. The first input terminal is coupled to the output terminal of the first edge delay circuit. The second input terminal is coupled to the first complementary output terminal. The first comparator output terminal is coupled to the second complementary output terminal. A second edge delay circuit has an input terminal, an output terminal, and a control input terminal. The input terminal is coupled to the second complementary output terminal. A second comparator has a first, second and third input terminal, an output terminal, and a control input terminal. The first input terminal is coupled to the output terminal of the second edge delay circuit.

Abstract: A local clock used for synchronizing events in an industrial control system may be synchronized with a master clock according to synchronization signals received at a first period. Updating of the local clock is performed on a more frequent basis than the receipt of the update signals. By using the update signals to derive an error value which is incrementally applied to the clock at a much higher rate, the maximum deviation is reduced. The system works with clocks having discrete frequency outputs by adjusting the update rate so as to effectively produce a continuously variable output frequency for the local clock over an interval equal to the update rate.