Patents Examined by Stacy A. Whitmore
  • Patent number: 10446581
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: October 15, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 10423746
    Abstract: A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: September 24, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srikanth Pam, Yudhister Satija, Pradeep Kumar Chawda, Makram Mounzer Mansour, Robert Mason Hanrahan, Jeffrey Robert Perry
  • Patent number: 10411517
    Abstract: A wireless power transfer method for a wireless power transfer apparatus using full and half-bridge inverter topologies includes detecting whether or not a wireless power receiver is present within a range of power being transferrable in a wireless manner, transmitting a detection signal to the wireless power receiver, receiving at least one of identification information and setting information from the wireless power receiver, receiving a control error packet from the wireless power receiver, and controlling an amount of power to be transferred by using the combination of a driving frequency, a duty cycle or a power signal phase to the full or half-bridge inverter.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: September 10, 2019
    Assignee: LG ELECTRONICS INC.
    Inventors: Jihyun Lee, Hyunbeom Lee, Yongcheol Park, Jaesung Lee
  • Patent number: 10409943
    Abstract: A computer implemented method for routing preservation is presented. The method includes decomposing, using the computer, a geometric relationship between a first module, a second module, and a routing path of a source layout, when the computer is invoked to route the solution path. The method further includes disposing, using the computer, the routing path in a solution layout in accordance with the geometric relationship. The solution layout is not defined by a scaling of the source layout.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: September 10, 2019
    Assignee: SYNOPSYS, INC.
    Inventors: Tung-Chieh Chen, Po-Cheng Pan, Ching-Yu Chin, Hung-Ming Chen
  • Patent number: 10394996
    Abstract: Via array placement on a printed circuit board (PCB) outline including receiving, by a PCB design module, via array data from a user; generating, by the PCB design module, a via array based on the via array data from the user, including placing the via array on the PCB outline, wherein the via array comprises a grid of vias; detecting, by the PCB design module, that a first PCB element has been placed on top of a first portion of the via array on the PCB outline; removing, by the PCB design module, the first portion of the via array under the first PCB element, wherein a second portion of the via array remains on the PCB outline after removing the first portion of the via array; and generating, by the PCB design module, a PCB design document using the PCB outline and the second portion of the via array.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Michael A. Christo, David L. Green, Julio A. Maldonado, Diana D. Zurovetz
  • Patent number: 10380291
    Abstract: A system and method for web-based interface design tool is provided. The design tool enables system designers to quickly and independently design a custom serial-link interface. The system provides interface selection and signal integrity analysis. An interface selection may interact with system designers to prompt for a set of selection criteria such as data-rate, supply rail, standard protocol, and intended application. An intelligent search engine screens through a large interface products database based on the selection criteria and provides designers with a list of devices that potentially meet the design criteria. The performance of the custom system with the selected device can be evaluated by using a web-based IBIS-AMI standard-compliant signal integrity simulator. A designers can have options to manually fine tune selected devices' parameters to iterate through different settings to determine the robustness of the solution.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: August 13, 2019
    Assignee: Texas Instruments Incorporated
    Inventors: Kian Haur Chong, Makram Monzer Mansour, Ashwin Vishnu Kamath, Srikanth Pam, Yudhister Satija, Nithya Narayanaswamy, Khang Duy Nguyen, Pavani Jella, Jeff Perry, Pradeep Kumar Chawda
  • Patent number: 10381863
    Abstract: An energy storage device for a photovoltaic system includes: at least one first energy store which has a first cycle stability; at least one second energy store which has a second cycle stability, the first cycle stability being higher than the second cycle stability; and a control device which is designed to discharge the first energy store in a first operating mode and to discharge the second energy store in a second operating mode.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: August 13, 2019
    Assignee: ROBERT BOSCH GMBH
    Inventor: Johanna May
  • Patent number: 10372848
    Abstract: A method and an apparatus for providing a safe operation of a technical system including a plurality of system components. The method includes the steps of: a) providing a safety analysis model matured by knowledge about former implementations of the respective system components in different context, b) whereby system components' dependencies are modeled by connecting inports with outports of the respective system components and/or vice versa, c) whereby at least one or a plurality of such in and/or outports are associated with input failure modes and/or output failure modes, d) characterized in automatically uncovering inconsistencies caused by at least one system component to be integrated in connection with at least another system component whereby the input and/or output failure mode of the system component carries the knowledge from another implementation into the context.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: August 6, 2019
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Kai Höfig, Marc Zeller
  • Patent number: 10366339
    Abstract: Quantum circuits and circuit designs are based on factorizations of diagonal unitaries using a phase context. The cost/complexity of phase sparse/phase dense approximations is compared, and a suitable implementation is selected. For phase sparse implementations in the Clifford+T basis, required entangling circuits are defined based on a number of occurrences of a phase in the phase context in a factor of the diagonal unitary.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: July 30, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Alexei Bocharov, Krysta Svore, Jonathan Welch
  • Patent number: 10366193
    Abstract: According to exemplary embodiments, a system and method for automated system power supply design is provided. The system and method enables circuit designers to quickly and independently design complicated single or multi rail power supply systems including multiple loads and sequencing requirements. The power solutions offered to designers may include all required power supplies to power up the loads including sequencers and load switches. The power supply design system may be implemented on a standalone processing unit, a distributed computing network, internet based web application, or among various other network applications.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: July 30, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Satyanandakishore Venkata Vanapalli, Abishek Gupta, Dien Mac, Andres Preciado, Pavani Jella, Wanda Carol Garrett, Marcos Lopez, Tim Reyes
  • Patent number: 10361175
    Abstract: The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: July 23, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Yi Xu, Xing Hu, Yuan Xie
  • Patent number: 10355494
    Abstract: A method and apparatus are provided for determining, by a wireless power transmitter, whether a wireless power receiver is removed from a wireless power network managed by the wireless power transmitter. The method includes transmitting a command signal to report power information of the wireless power receiver at stated periods; determining whether a report signal corresponding to the command signal is received from the wireless power receiver; and determining that the wireless power receiver is removed from the wireless power network, if the report signal is not received after transmitting the command signal a predetermined number of times at the stated periods.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Kyung-Woo Lee, Kang-Ho Byun, Se-Ho Park
  • Patent number: 10345694
    Abstract: Approaches herein provide model-based generation of dummy features used during processing of a semiconductor device (e.g., during a self-aligned via process). Specifically, at least one approach includes: generating a set of dummy features in proximity to a set of target features in a mask layout, evaluating a proximity of the set of dummy features to a metal layer of the semiconductor device, and removing a portion of the set of dummy features that is present within an established critical distance between the set of dummy features and the metal layer. Target design printability is further enhanced during photolithography by performing one or more of the following: merging two or more dummy features of the set of dummy features, and increasing a distance between adjacent dummy features of the set of dummy features by modifying a geometry of one or more of the set of dummy features.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: July 9, 2019
    Assignee: BLOBALFOUNDRIES INC.
    Inventor: Ayman Hamouda
  • Patent number: 10339260
    Abstract: A method of determining a characteristic of a guiding template for guiding self-assembly of block copolymer to form an entirety of a design layout, or a portion thereof, including a plurality of design features, each design feature including one or more elemental features, the method including selecting a characteristic of a guiding template for each of the one or more elemental features of the plurality of design features from a database or a computer readable non-transitory medium, the database or the computer readable non-transitory medium storing a characteristic of a guiding template for each of the one or more elemental features, and determining the characteristic of the guiding template to form the entirety of the design layout, or the portion thereof, by combining the selected characteristic of the guiding template for the one or more elemental features for each of the plurality of design features.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: July 2, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Bart Laenens, Sander Frederik Wuister
  • Patent number: 10338138
    Abstract: A Design-for-testability method based on composition of test patterns copes with increasing test complexity and cost metric of a large system. System-level structural test patterns from test patterns of constituent subsystems, cores and design IPs are constructed without requiring their design netlists. The delivered test patterns can be utilized 100% in the testing of system. The system-level test pattern is delivered to the device under test, the subsystem test patterns can be scheduled and applied continuously without being interleaved by test deliveries until all of the subsystem test patterns are exercised. Absence of design netlist requirement allows uniform integration of external and internal IPs regardless of availability of test isolation logic or design details. Concurrent test of constituents and their mutual independence in scan operations allows implicit distribution of test protocol signals such as scan enable (SE) and the scan clocks. The method enables at-speed testing of memory shadow logic.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: July 2, 2019
    Inventor: Chinsong Sul
  • Patent number: 10339252
    Abstract: A method for enhancing a chip layout may include obtaining the chip layout including a first layer including first and second tracks, a first route occupying the first track, and an open net including open terminals. The method may further include grouping the open terminals into at least a first subset of open terminals, calculating, based on the first subset, a region of interest (ROI), determining that neither the first track nor the second track within the ROI can be used to connect all the open terminals in the first subset, determining that the first track can be used to connect all the open terminals in the first subset after moving the first route from the first track to the second track, moving, the first route from the first track to the second track, and attempting to connect all the open terminals in the first subset using the first track.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 2, 2019
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Tanushriya Singh, Akshay Sharma, Duo Ding, Chen Dan Dong
  • Patent number: 10333333
    Abstract: A wireless charging table comprising a table top having an upper surface upon which one or more electronic devices can be placed, a wireless charging transmitter positioned under the upper surface of the table top, the wireless charging transmitter comprising a plurality of transmitter coils that define a charging region at the upper surface of the table top, and a power distribution system operatively coupled to the wireless charging transmitter, the power distribution system configured to receive power from an alternating current (AC) power source and distribute power to the wireless charging transmitter. The plurality of transmitter coils include at least a first transmitter coil comprising: a first loop portion; a second loop portion; and a crossing portion comprising overlapping conductive paths that electrically couple the first loop portion.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: June 25, 2019
    Assignee: Apple Inc.
    Inventors: David W. Ritter, David B. Kosecoff, David S. Kumka, Madhusudanan Keezhveedi Sampath, Steven Charles Michalske, Tavys Q. Ashcroft, Aditya Rao, Ariadne Smith
  • Patent number: 10331832
    Abstract: A method for floating node reduction uses a capacitance matrix that specifies coupling capacitances between signal nodes and floating nodes of an interconnect structure. Random walks are performed from a first signal node to the other signal nodes, wherein each of the random walks traverses one or more of the floating nodes. Each of the random walks is directed based on probabilities derived from the coupling capacitances of the capacitance matrix. A count is maintained for each of the other signal nodes, wherein each count specifies a number of the random walks that end on the corresponding signal node. The indirect coupling capacitance from the first signal node to a second signal node is selected to correspond with the total indirect coupling capacitance of the first signal node, times the count associated with the second signal node, divided by the total number of random walks.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: June 25, 2019
    Assignee: Synopsys, Inc.
    Inventors: Alexei Svizhenko, Arindam Chatterjee, Arthur B. Nieuwoudt
  • Patent number: 10325053
    Abstract: A method and apparatus for matching the lengths of traces of differential signal pairs. The method includes determining that a first trace is longer than a second trace and modifying the second trace so that the length is substantially equal to the length of the first trace. In some implementations, the second trace can be modified by replacing one or more sections of the trace with two line segments that are substantially equal in length and meet at a vertex that is less than 180 degrees.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 18, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Lin Shen, Yongming Xiong, Stephen Ong, Shahbaz Mahmood
  • Patent number: 10325045
    Abstract: A computer system for estimating timing convergence using assertion comparisons. The computer system receives predefined golden assertions associated with a macro to be tested. The computer system executes the macro to obtain current feedback assertion values. The computer system calculates one or more metrics based on a comparison between the current feedback assertion values and values of one or more different sets of assertions. The computer system estimates a time to convergence based on the one or more calculated metrics. The computer system generates a schedule based on the estimated time to convergence.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ofer Geva, Yaniv Maroz, Limor Plotkin, Shiran Raz