Abstract: A power-on-reset circuit includes first to third first-conductive-type MOSFETs, a second-conductive-type MOSFET, a capacitance, and first to third resistances. In the power-on-reset circuit, whether a reset signal is supplied to an external circuit is determined by threshold voltages of the MOSFETs and independent on the building-up speed of the power supply voltage.

Abstract: A liquid crystal display device includes a base supporting a laminate which has an LC-layer (liquid crystal layer) formed of polymeric material holding micro-volumes of liquid crystal material, and a conductive layer on one surface of the LC-layer, the other surface of the LC-layer being substantially conductor-free, and apparatus for transitory application of potential through the LC-layer to the conductive layer to produce an image. The LC-layer has at least about 50% by weight of the polymeric material and less than 50% of the liquid crystal material by weight of the LC-layer, and the duration of image retention after transitory application of potential ceases is significantly extended.

Abstract: A noninverting transistor switch having only three terminals includes in one embodiment first, second and third terminals, a depletion mode field effect transistor (FET) having drain and source electrodes that define a current path in the transistor and are connected to the third and second terminals respectively and a gate electrode for controlling the current flow in the transistor current path. A negative voltage converter having an input electrode, an output electrode and a return electrode has its output electrode coupled to the gate electrode in the FET its return electrode being coupled to the source electrode and its input electrode coupled to the first terminal. In operation, the current flow between the drain and source electrodes will be high when a low signal is applied to the input electrode with respect to the source electrode and will be lower when a higher signal is applied to the input electrode with respect to the source electrode.

Abstract: A control circuit for coupling an AC (alternating current) source to a load comprises a MOSFET transistor having source and drain electrodes with a main conductor channel therebetween and a control electrode for controlling conduction ibn the main conduction channel. The control circuit further comprises a capacitor arrangement, the MOSFET transistor having the main conduction channel thereof coupled with the capacitor arrangement in a series circuit for coupling therethrough the AC source to the load.

Abstract: In a sampling mode, a servo signal sampling and holding switch (4.sub.a) and a reference voltage sampling and holding switch (30.sub.a) are turned off, so that transistors (Q.sub.7a, Q.sub.5a) are turned on. In response to on states of the transistors (Q.sub.7a, Q.sub.5a), capacities (C.sub.3a, C.sub.30a) are charged with the peak voltage (V.sub.ref +(1/2)V.sub.s) of a servo signal and a reference voltage (V.sub.ref), respectively. In a holding mode, the sampling and holding switches (4.sub.a, 30.sub.a) are turned on, so that the transistors (Q.sub.7a, Q.sub.5a) are turned off. the charging voltages (D, E) of the capacitors (C.sub.3a, C.sub.30a) are discharged through post-stage buffers (5.sub.a, 3.sub.a), so that they include offsets which are canceled through a subtractor (6.sub.a).

Abstract: A bipolar ECL latch or flip-flop circuit of the isolated differential feedback type provides a high level of alpha particle immunity, without unduly affecting the propagation delay, power dissipation or circuit area in an integrated circuit device. A pair of latch transistors having differential input are used, with common emitters coupled to a clocked current source. The latch outputs are coupled back to a pair of holding transistors by two emitter follower feedback transistors. The holding transistors have a common emitter connection to a current source clocked inversely to that of the current source for the latch transistors, so the state of the latch is held by the holding transistors. The amplification of the feedback transistors is reduced so that the speed with which the transistor can react to transient noise such as that produced by an alpha hit is reduced.

Abstract: An electrical assembly including a digital logic circuit, an analogue processing circuit and an analogue power circuit is connected to test equipment. Test data from the equipment is supplied to the circuits via a shift register divided into three serial portions. One portion is connected between the digital circuit and the processing circuit, another portion is connected between the processing circuit and the power circuit, the final portion being connected at the output of the power circuit. The portions can isolate the circuits from each other and supply test data to the circuit under test. The test data output from the circuit is clocked along the register to its output.

Abstract: A level changing semiconductor integrated circuit includes two current paths in which emitters of first and second bipolar transistors are each connected in series to one terminal of first and second MOSFETs, respectively. The current paths are disposed between a high-potential power source and a low-potential power source. Gates of the first and second MOSFETs are cross-connected to the emitters of the bipolar transistors of opposite current paths. The emitters of the first and second bipolar transistors provide output signals. At least two different types of input signals having different signal levels are simultaneously applied to respective input units of the current paths.

Abstract: A self-adjusting impedance matching driver for a digital circuit. The driver has both a pull-up gate to VDD and a pull-down gate to ground. An array of gates is provided in parallel with each of the pull-up gate and the pull-down gate, with any one or more of such gates being selectively enabled in response to circuit means that monitors the impedance match between the output of the driver and the network it drives. By enabling selectively such gates, any impedance mismatch can be minimized. The selective enablement may be done only at power up, and thereafter only if the driven network is changed substantially.

Abstract: The present invention provides a switch in which a liquid-crystal panel is arranged on the top side of a push-button so that such information as characters, symbols and figures is capable of being displayed, wherein a plurality of light-emitting bodies which emit light in a number of colors are arranged below the light-emitting panel so that the color of the liquid-crystal panel is capable of being changed. The liquid-crystal panel on the top surface of the push-button is white in color, a diffusing plate is disposed below the liquid-crystal panel, and the light-emitting bodies are arranged to oppose the periphery of the diffusing plate. As a result, the color of the overall display portion on the top surface of the push-button can be changed.

Abstract: A circuit for trimming the input offset voltage of an input stage of an op amp includes variable resistors (20, 24) for providing variable voltages in series with the input voltage of the op amp. The voltage drop across the variable resistors is adjusted to compensate for any base-emitter voltage mismatches of the input transistors (12, 14) thereby making the input offset voltage of the op amp equal to zero. Further, the variable resistors can be replaced by resistive networks (40, 42) such that the resistive networks can be adjusted to provide an input stage with a zero temperature coefficient as well as a zero input offset voltage.

Abstract: A shift register circuit includes a logical operator which is added to an output terminal of a latch portion and takes a logical operation of input and output signals of the latch portion and outputs its result as a bit signal. The signal of a bit component is shifted to a higher order bit every half of the period of a clock signal so that a shifting speed thereof can be made two times faster than that in a conventional shift register circuit. It may be arranged such that a higher order bit section starts to output a signal after the preceding lower order bit section outputs a low level signal thereby enabling to avoid the signals outputted by the bit sections neighboring to each other becoming simultaneously intermediate values between a high level and a low level. Also, the bit sections may be cascade-connected such that each of the sections takes a logical operation of the input and output signals of the latch portion. In view of the configuration involved, the number of elements per bit can be reduced.

Abstract: A liquid-crystal phase modulator array, comprising a planar electrode on one glass support and an array of finger electrodes on the other glass support with a nematic liquid filling the gap between the two supports. The alignment layer between the finger electrodes and the liquid crystal is rubbed to have an alignment direction extending along the finger electrodes and prependicular to the gap between them. The alignment layer between the planar electrode and the liquid crystal is rubbed in the anti-parallel direction. Voltages are selectively applied to different ones of the finger electrodes to provide a phase modulator array for light passing through the assembly. The alignment direction of the invention eliminates ragged edges adjacent the edges of the finger electrodes arising from an instability. Thereby, the finger electrodes can be made much narrower, and more pixels can be included in the array. The phase modulator of the invention can be advantageously used in a Fourier optical pulse shaper.

Abstract: A BICMOS passgate circuit (PSGT3) (PSGT3A) for use in latches and flip-flops incorporates a bipolar output circuit (Q1,Q3) comprising a bipolar pullup transistor element (Q1) and a bipolar pulldown transistor element (Q3) coupled to the passgate output (V.sub.OUT) for transient charging and discharging of load capacitance (C.sub.L) at the passgate output (V.sub.OUT). The bipolar output circuit provides increased sinking and sourcing output drive current and .beta. amplification of sinking and sourcing drive current at the passgate output V.sub.OUT in response to data signals at the passgate intput (V'.sub.IN) in the transparent operating mode. An MOS input logic circuit coupled to the passgate input (V'.sub.IN) includes clock signal inputs (CP,CP) for implementing transparent and blocking operating modes.

Abstract: A multipurpose liquid crystal display, suitable for use as a reflective display and as overhead projection panel, includes (a) a first transparent electrode means; (b) a second transparent electrode means; (c) a display medium positioned between the first and second transparent electrode means, which display medium is switchable between a first state in which incident light is scattered and a second state in which the amount of such scattering is reduced; (d) a retroreflector removably positioned behind the second transparent electrode means; and (e) means for removably positioning the retroreflector behind the second transparent electrode. Preferably, the display medium comprises positive dielectric anisotropy, operationally nematic liquid crystals dispersed in a containment medium.

Abstract: In a color liquid crystal display device of the invention, light-blocking members of predetermined configurations (characters, graphics etc.) are disposed on the surface of one side of a liquid crystal display element, that is to say the surface on the side opposite to the light source, and the predetermined configurations are displayed on the color liquid crystal display device by blocking the light from the light source with the light-blocking members. Further, a light-scattering plate is disposed between the light source and the liquid crystal display element, or between the liquid crystal display element and the light-blocking members. It is possible to allow transmission of a part of the light blocked by the light-blocking members by scattering the light which is transmitted through the liquid crystal display element with the arrangement of the light-scattering plate.

Abstract: An optical modulation device includes scanning electrodes and signal electrodes disposed opposite to and intersecting with the signal electrodes, and an optical modulation material disposed between the electrodes, a pixel being formed at each intersection of the electrodes and showing a contrast depending on the polarity of a voltage applied thereto.

Abstract: An LED pulse shaping circuit is disclosed which is capable of providing improved rise time (using current peaking) and fall time (using charge extraction). The pulse shaping circuit consists of a conventional differential current switch coupled to a pair of switching elements and resistance elements. A first switching element is activated at the beginning of a pulse to provide for an initially increased drive current to the LED, the value of a first resistance element used to determined the level of the increased drive current. The current peaking thus results in decreasing the rise time of the LED. The remaining switching element and resistance are utilized, in conjunction with the differential current switch, to provide a reverse current flow through the LED at the end of the pulse. The charge extraction thus results in decreasing the fall time of the LED.

Abstract: A spatial-light modulator provided with a first electrode formed by a transparent member that receives irradiation of write light corresponding to an optical image in order to form a charge image; a second electrode formed by a transparent member to receive read light irradiated in order to read a formed charge image and to discharge output light equivalent to a read charge image; an optical modulation layer provided to the first electrode side of the second electrode and formed by polymer dispersed liquid crystal material in order to change the intensity distribution of the read light irradiated via the second electrode in accordance with an electrical field intensity distribution due to the charge image; a photoconductive member provided between the first electrode and the optical modulation layer, formed with two different materials of at least amorphous silicon carbide and amorphous silicon as the primary components, and formed in a plural number of layers and having a laminated structure having an optica

Abstract: In an image processing apparatus employing a liquid crystal display, a light source is provided. The light emitted from the light source and external light are selectively utilized as the back light of the liquid crystal display. A driving circuit receives an image signal and outputs a drive signal, in accordance with the white balance of the light source. A white balance sensor is further provided in the image processing apparatus. When the external light is used as the back light, the drive signal to be supplied to the liquid crystal display is compensated so that the hue of the displayed image becomes optimum.