Abstract: An etching method prepares a substrate having laminated films including a first film and a second film that are alternately laminated, and a mask on the laminated films, and etches the laminated films by plasma of a process gas including a carbon and fluorine-containing gas. The carbon and fluorine-containing gas includes an unsaturated bond of C, and a CF3 group.

Abstract: A semiconductor structure processing method and forming method are provided. The semiconductor structure processing method includes the steps of: providing a semiconductor substrate, which is provided with feature portions having a mask layer on their top surfaces; ashing a semiconductor structure comprising the semiconductor substrate, the feature portions and the mask layer; removing the mask layer; cleaning the semiconductor structure, and forming an oxide layer on surfaces of the feature portions after the feature portions are cleaned; drying the semiconductor structure; and removing the oxide layer. During drying, one feature portion of at least one group of adjacent feature portions is inclined towards a feature portion adjacent thereto, and a distance between the inclined feature portion and the feature portion adjacent thereto after drying is smaller than a distance there between before drying.

Abstract: A method of preparing a polishing composition includes forming a dispersion solution containing ceria particles, and irradiating ultraviolet (UV) light onto the dispersion solution.

Abstract: A manufacturing method of a pad conditioner by reverse plating is disclosed. The method comprises: forming a first plating layer on a temporary substrate to have multiple recesses; forming a second adhesive photosensitive film on the first plating layer; putting grains into the recesses; forming a first filling layer to support the grains; forming a second filling layer to support the grains; removing the second adhesive photosensitive film and forming a second boundary layer on the entire surface; forming a second plating layer on the second boundary layer; removing the temporary substrate and attaching a final substrate to the second plating layer; removing the first boundary layer and the first plating layer; removing the second boundary layer excluding a portion not exposed to the outside; and forming a third plating layer on an entire surface opposite to the final substrate to support the grains.

Abstract: The present invention relates to methods of delayering a semiconductor integrated circuit die or wafer. In at least one aspect, the method includes exposing a die or wafer to plasma of an etching gas and detecting exposure of one or more metal layers within the die. In one aspect of the invention, the plasma of the etching gas is non-selective and removes all materials in a layer at about the same rate. In another aspect of the invention, two different plasmas of corresponding etching gases are employed with each plasma of the etching gas being selective, thus necessitating the sequential use of both plasmas of corresponding etching gases to remove all materials in a layer.

Abstract: A method of patterning a substrate is provided. The method includes modifying a surface of a metal-containing layer formed over a substrate positioned in a processing region of a processing chamber by exposing the surface of the metal-containing layer to plasma effluents of a chlorine-containing gas precursor and an oxygen-containing gas precursor to form a modified surface of the metal-containing layer. The method further includes directing plasma effluents of an inert gas precursor towards the modified surface of the metal-containing layer. The plasma effluents of the inert gas precursor are directed by applying a bias voltage to a substrate support holding the substrate. The method further includes anisotropically etching the modified surface of the metal-containing layer with the plasma effluents of the inert gas precursor to form a first recess having a first sidewall in the metal-containing layer.

Abstract: Provided are a method for polishing a silicon substrate according to which PID can be reduced and a polishing composition set usable in the polishing method. The silicon substrate polishing method provided by this invention comprises a stock polishing step and a final polishing step. The stock polishing step comprises several stock polishing sub-steps carried out on one same platen. The several stock polishing sub-steps comprise a final stock polishing sub-step carried out while supplying a final stock polishing slurry PF to the silicon substrate. The total amount of the final stock polishing slurry PF supplied to the silicon substrate during the final stock polishing sub-step has a total weight of Cu and a total weight of Ni, at least one of which being 1 ?g or less.

Abstract: A method for forming a stair-step structure in a stack on a substrate is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is provided in a plurality of cycles wherein each cycle comprises etching a SiO2 layer and etching a SiN layer. Etching a SiO2 layer comprises flowing a SiO2 etching gas into the plasma processing chamber, wherein the SiO2 etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SF6 and NF3, generating a plasma from the SiO2 etching gas, providing a bias, and stopping the SiO2 layer etch. The etching a SiN layer comprises flowing a SiN etching gas into the plasma processing chamber, comprising a hydrofluorocarbon and oxygen, generating a plasma from the SiN etching gas, providing a bias, and stopping the SiN layer etch.

Abstract: According to one embodiment, a registration mark includes a first step portion and a second step portion. The first step portion includes a plurality of first steps which descend step by step in a first direction from a surface of a substrate or a layer formed on the substrate. The second step portion includes a plurality of second steps which descend step by step from the surface in a second direction different from the first direction and have the same number as the number of the plurality of first steps, is spaced apart from the first step portion, and is disposed rotationally symmetrically to the first step portion.

Abstract: A substrate processing method includes preparing a substrate including an etching target film and a mask; etching the etching target film through the mask by plasma; and heat-treating the substrate at a preset temperature after the etching of the etching target film.

Abstract: A method for forming a semiconductor structure includes providing a substrate, forming a stop layer over a surface of the substrate, forming a dielectric layer over a surface of the stop layer, forming a first opening in the dielectric layer and exposing a portion of the stop layer, modifying the portion of the stop layer exposed at a bottom of the first opening to form a modification layer, and removing the modification layer to form a second opening from the first opening.

Abstract: A substrate processing method includes etching a substrate having a first film and a second film at a first etching rate; changing an etching rate from the first etching rate to a second etching rate; and etching the substrate at the second etching rate.

Abstract: Provided is a method that is for polishing a silicon wafer by a polishing device using a carrier holding the silicon wafer, and that can reduce wear on the carrier. In this polishing method, a polishing liquid used in the polishing device contains 0.1-5 mass %, in terms of the concentration of silica, silica particles comprising: silica particles (A) having an average primary particle size of 4-30 nm as measured by BET, and having an (X2/X1) ratio of 1.2-1.8, where X2 (nm) represents an average particle size along the major axis thereof as calculated from a perspective projection image obtained using an electron beam, and X1 (nm) represents the average primary particle size as measured by BET; and silica particles (B) having an average primary particle size of more than 30 nm but not more than 50 nm as measured by BET, and having a (X2/X1) ratio of 1.2-1.

Abstract: A processing method for a wafer having a chamfered portion at a peripheral edge includes a holding step of holding the wafer by a holding table, and a chamfer removing step of rotating the holding table while causing a first cutting blade to cut into the peripheral edge of the wafer while supplying a cutting liquid from a first cutting liquid supply nozzle to cut the peripheral edge of the wafer. In the chamfer removing step, a second cutting unit is positioned at a position adjacent to the first cutting unit at such a height that a second cutting blade does not make contact with the wafer and on the side of the center of the wafer as compared to the first cutting unit, and the cutting liquid is supplied from a second cutting liquid supply nozzle.

Abstract: Plasma-assisted methods and apparatus are disclosed. The methods and apparatus can be used to provide activated species formed in a remote plasma unit to a reaction chamber to assist ignition of a plasma within a reaction chamber coupled to the remote plasma unit.

Abstract: Exemplary processing methods may include forming a plasma of a silicon-containing precursor. The methods may include depositing a flowable film on a semiconductor substrate with plasma effluents of the silicon-containing precursor. The semiconductor substrate may define a feature within the semiconductor substrate. The methods may include forming a plasma of a hydrogen-containing precursor within the processing region of the semiconductor processing chamber. A bias power may be applied to the substrate support from a bias power source. The methods may include etching the flowable film from a sidewall of the feature within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor. The methods may include densifying remaining flowable film within the feature defined within the semiconductor substrate with plasma effluents of the hydrogen-containing precursor.

Abstract: Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic metal oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates. Chemical additives comprise at least one nitrogen-containing aromatic heterocyclic compound and at least one non-ionic organic molecule having more than one hydroxyl functional group organic.

Abstract: To provide a wavelength selection method or a plasma processing method to achieve accurate detection of residual thickness or etching amount, there is provided a plasma processing method, in which a processing object wafer is disposed within a processing chamber in the inside of a vacuum container, and plasma is generated by supplying a processing gas into the processing chamber and used to process a processing-object film layer beforehand formed on a surface of the wafer, and at least two wavelengths are selected from among wavelengths with large mutual information in emission of a plurality of wavelengths of plasma generated during processing of the processing-object film layer, and a temporal change in the emission of at least the two wavelengths is detected, and an endpoint of the processing of the film layer is determined based on a result of the detection.

Abstract: A CMP slurry composition for polishing a tungsten pattern wafer and a method of polishing a tungsten pattern wafer, the composition including a solvent, the solvent including a polar solvent or a non-polar solvent; an abrasive agent; and an oxidizing agent, wherein the abrasive agent includes silica modified with an amino silane that includes three nitrogen atoms.

Abstract: A method for patterning a material layer on a substrate includes forming a hard mask layer on a material layer disposed on a substrate, and etching the material layer through the hard mask layer by simultaneously supplying an etching gas mixture and an oxygen containing gas. The etching gas mixture is supplied continuously and the oxygen containing gas is pulsed.