Patents Examined by Stephen C. Elmore
  • Patent number: 8601223
    Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced page table entries are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can redirect one or more pending page table entry fetch requests to an appropriate coalesced page table entry.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: December 3, 2013
    Assignee: Nvidia Corporation
    Inventor: Lingfeng Yuan
  • Patent number: 8103851
    Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: January 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb
  • Patent number: 8082405
    Abstract: In an enhanced dynamic address translation facility a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are used to access a segment table entry containing a format control field and an access validity field. If the format control field is enabled, the segment table entry further contains an access control field and a fetch protection field and a segment-frame absolute address. Fetch operations from the desired block of data are permitted if the program access key associated with the virtual address is equal to the segment access control field.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: December 20, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dan F. Greiner, Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles E. Webb
  • Patent number: 8055875
    Abstract: A partition wizard allows automatically defining from a set of system requirements a solution profile that defines a combination of hardware and software in multiple logical partitions to satisfy the performance objectives. The solution profile may be used by an order processing system to automatically generate an order for a target computer system. The solution profile may also be used by a hardware management console to automatically create logical partitions on the target computer system, then may be used by an operating system install engine to automatically install a desired operating system in each of the logical partitions on the target computer system and to automatically install desired software into each of the logical partitions in the target computer system. The solution profile may also be used to manage the target computer system.
    Type: Grant
    Filed: March 15, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: David Joseph Gimpl, Kyle Lane Henderson, Kent LeDel Hofer, Cale T. Rath, George James Romano, Tammy Lynn Van Hove
  • Patent number: 8041905
    Abstract: A method for dynamically allocating control of a storage device, the method comprising receiving an access request from a first computer requesting access to a storage device; directing, based upon the access request, a first storage controller computer to assume an inactive state with respect to control of the storage device; and directing, based upon the access request, a second storage controller computer to assume an active state with respect to control of the storage device.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: October 18, 2011
    Assignee: CommVault Systems, Inc.
    Inventors: Varghese Devassy, Rajiv Kottomtharayil, Manoj Kumar Vijayan Retnamma
  • Patent number: 8032718
    Abstract: A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy copy; copying, to the first piece of removable storage media, data associated with the first storage policy copy; and copying, to the first piece of removable storage media, data associated with the second storage policy copy.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: October 4, 2011
    Assignee: CommVault Systems, Inc.
    Inventors: Rajiv Kottomtharayil, Parag Gokhale, Anand Prahlad, Manoj Kumar Vijayan Retnamma, David Ngo, Varghese Devassy
  • Patent number: 8015368
    Abstract: Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: September 6, 2011
    Assignee: Siport, Inc.
    Inventors: Sridhar Sharma, Binuraj Ravindran, Jeffrey V. Hill
  • Patent number: 8010761
    Abstract: In a storage system, one or more storage apparatuses provide a management computer with a first volume for storing data from the management computer, provide a host computer with a second volume for storing data from the host computer, and manage a volume address for the one or more storage apparatuses to manage the first volume and the second volume in the one or more storage apparatuses. The management computer issues a command specifying an arbitrary volume address to the one or more storage apparatuses, and designates, when receiving a normal response from the arbitrary volume address, a volume with the arbitrary volume address as the second volume.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: August 30, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Nobuhiro Maki, Takeyuki Imazu, Hiroshi Yamamoto
  • Patent number: 8006055
    Abstract: Protection entries and techniques for providing fine granularity computer memory protection are described herein. A method of protecting a computer memory may include separating or parsing the computer memory, containing data or code, into blocks and creating protection entries for each block. The protection entries optionally include a reference field for identifying a block of memory, and a protection field for specifying one or more levels of access to the identified block of memory. The protection entries may then be used to pass messages between various system entities, the messages specifying one or more levels of access to the one or more blocks of memory or code.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: August 23, 2011
    Assignee: Microsoft Corporation
    Inventors: Bradley M Waters, Niklas Gustafsson
  • Patent number: 8001358
    Abstract: A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideki Matsuyama, Masayuki Daitou
  • Patent number: 7996633
    Abstract: Systems and techniques for sequencing transactions and operations. In one aspect, an article includes one or more machine-readable media storing instructions operable to cause one or more machines to perform operations. The operations include identifying a delta of a first data store, and replicating the delta, including the transaction, to a second data store. The delta comprising a collection of changes to the first data store since a previous replication. The delta includes a transaction that began before the previous replication but did not commit before the previous replication replicated data from the first data store.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: August 9, 2011
    Assignee: SAP AG
    Inventors: Peter K. Zimmerer, Stefan Dipper, Stefan Biedenstein, Rainer Brendle
  • Patent number: 7996637
    Abstract: Data written in the primary logical volume of the first storage device are transmitted to the third storage device via the second storage device, the data being written in the same location as the primary logical volume within the secondary logical volume in the third storage device; when transmission of the data stops among the first to the third storage devices, the respective second storage device and the third storage device manage locations in the secondary logical volume where the data held thereby are to be written; and, when transmission of the data resumes among the first to the third storage devices, the locations in the secondary logical volume managed by the respective second and the third storage devices are aggregated, the data to be written in the respective aggregated location in the secondary logical volume being transmitted from the first storage device to the third storage device via the second storage device.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: August 9, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Shintaro Inoue, Katsuhiro Okumoto
  • Patent number: 7996611
    Abstract: Provided are a backup data management system and a backup data management method capable of facilitating the management of backup data that is multiplexed between different storage apparatuses. The backup data management system includes a storage apparatus having a volume to be used by a host computer, at least one storage apparatus having volumes, and a management computer. The management computer creates a copy pair so that a snapshot of the volume included in a backup group is stored in all the volumes included in the backup group, and sets all copy pairs included in the designated backup group to a PAIR status when there is a creation request of the snapshot of the volume.
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: August 9, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hirotaka Nakagawa, Masayasu Asano, Masayuki Yamamoto, Yuichi Taguchi
  • Patent number: 7991969
    Abstract: A method, system, apparatus, and computer-readable medium are provided for improved maintenance of metadata relating to a mass storage array. The metadata may comprise the data structures utilized by a thin provisioning system. When the metadata changes, such as in response to the modification of the underlying data, changed metadata is created in the memory. A parity block is then read from the row of the array where the changed metadata is to be stored. A new parity is calculated for the row using only the old metadata, the changed metadata, and the parity read from the stripe. The old metadata need not be read from disk expressly, as is usually done. Instead, the value that is present in memory before the metadata change is utilized directly to calculate the new parity. The changed metadata and the new parity are then written to the array.
    Type: Grant
    Filed: September 19, 2010
    Date of Patent: August 2, 2011
    Assignee: American Megatrends, Inc.
    Inventors: Paresh Chatterjee, Vijayarankan Muthirisavenugopal, Ajit Narayanan
  • Patent number: 7984242
    Abstract: A barrier for synchronizing program threads for a plurality of processors includes a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized. The filter is configured to monitor and selectively block fill requests for instruction cache lines. A method for synchronizing program threads for a plurality of processors includes configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: July 19, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jean-Francois C. P. Collard, Norman Paul Jouppi, Michael S. Schlansker
  • Patent number: 7984234
    Abstract: A memory control apparatus and a memory control method are provided to enable an effective utilization of buffer memory in a system LSI by comprising buffer memory for temporarily storing data stored in memory, and comprising the processes of: receiving an instruction to the memory; transmitting a buffer memory security-dedicated use packet for securing the capacity of memory in the buffer memory required by the instruction on the basis of the received instruction; receiving a buffer memory validation signal corresponding to the transmitted buffer memory security-dedicated use packet; and executing the received instruction on the basis of the received buffer memory validation signal.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: July 19, 2011
    Assignee: Fujitsu Limited
    Inventor: Shinichi Iwasaki
  • Patent number: 7979661
    Abstract: Methods, systems, and media to enhance memory overflow management by identifying a memory overflow condition associated with execution of a task and adjusting memory allocation for the task to attenuate the memory overflow condition are disclosed. In particular, embodiments reduce the impact of repetitious memory overflow conditions caused by a specific task by increasing the memory allocation for that task. The memory overflow may also be reported to a technical service provider to help the technical service provider identify and fix the code that is responsible for the memory overflow. Many embodiments monitor an extent of the overflow and determine an allocation correction term based upon the extent of the overflow. In some situations, application of a correction term to increase the memory allocation for the task may advantageously eliminate the cause of the memory overflow condition. In further situations, the impact of the memory overflow condition is attenuated.
    Type: Grant
    Filed: January 10, 2008
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventor: Marc Alan Dickenson
  • Patent number: 7979669
    Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.
    Type: Grant
    Filed: May 27, 2008
    Date of Patent: July 12, 2011
    Inventors: H. Peter Anvin, Guillermo J. Rozas, Alexander Klaiber, John P. Banning
  • Patent number: 7979644
    Abstract: A multiprocessor system comprises a plurality of system controllers, each of which performs a snoop processing regarding a cache device in its charge. The system controllers adjust the number of steps of a snoop pipeline for the snoop processing according to communication time with the other system controllers. The number-of-steps adjustment absorbs the difference of the communication time in the results of the snoop for each scale of the multiprocessor system. When a retrial is determined by an address conflict or the like in the snoop processing, each of the system controllers resubmits the access to be retried to the snoop pipeline after waiting until no other access which may cause an address conflict precedes. The resubmission timing prevents infinite repetition of the retrial of the snoop processing in the system controllers.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: July 12, 2011
    Assignee: Fujitsu Limited
    Inventors: Gou Sugizaki, Satoshi Nakagawa
  • Patent number: 7975096
    Abstract: A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: July 5, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Jiunn-Yeong Yang, Chien-Hua Chu, Kuo-Yi Cheng, Li-Chun Liang, Chih-Kang Yeh