Abstract: A method for increasing the efficiency of transferring packets of isochronous transfer type in USB 3.0 includes ignoring a packet of isochronous transfer type with an incorrect header. When the receiving end receives a packet of isochronous transfer type with an incorrect header, the receiving end does not send a retry signal to the transmitting end. Therefore, the transmitting end can more quickly transmit the following packets of isochronous transfer type.

Abstract: True bit level decoding of TTCM (Turbo Trellis Coded Modulation) of variable rates and signal constellations. A decoding approach is presented that allows for decoding on a bit level basis that allows for discrimination of the individual bits of a symbol. Whereas prior art approaches typically perform decoding on a symbol level basis, this decoding approach allows for an improved approach in which the hard decisions/best estimates may be made individually for each of the individual bits of an information symbol. In addition, the decoding approach allows for a reduction in the total number of calculations that need to be performed as well as the total number of values that need to be stored during the iterative decoding. The bit level decoding approach is also able to decode a signal whose code rate and/or signal constellation type (and mapping) may vary on a symbol by symbol basis.

Abstract: A digital broadcast transmitting/receiving system and a method for processing data are disclosed. The method for processing data may enhance the receiving performance of the receiving system by performing additional coding and multiplexing processes on the traffic information data and transmitting the processed data. Thus, robustness is provided to the traffic information data, thereby enabling the data to respond strongly against the channel environment which is always under constant and vast change.

Abstract: Embodiments of the present invention relate to systems, methods and computer storage media for erasure coding data in a distributed computing environment. A sealed extent is identified that is comprised of two or more data blocks and two or more index blocks. The sealed extent is optimized for erasure coding by grouping the two or more data blocks within the optimized sealed extent together and grouping the two or more index blocks within the optimized sealed extent together. The optimized extent may also be erasure coded, which includes creating data fragments and coding fragments. The data fragments and the coding fragments may also be stored in the distributed computing environment. Additional embodiments include monitoring statistical information to determine if replication, erasure coding or a hybrid storage plan should be utilized.

Abstract: LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.

Abstract: In one embodiment, a reconfigurable cyclic shifter is selectively configurable to operate in (i) five-bit mode to cyclically shift N five-bit messages by up to N degrees or (ii) ten-bit mode to cyclically shift N ten-bit messages by up to N degrees. The reconfigurable cyclic shifter has two five-bit N/2-way non-reconfigurable cyclic shifters. The two non-reconfigurable cyclic shifters together, without additional hardware, do not perform N degrees of cyclic shifting. Thus, five-bit and ten-bit reordering hardware is provided that enables the reconfigurable cyclic shifter to perform up to N degrees of cyclic shifting in the five- and ten-bit modes, respectively. In the five-bit mode, the N five-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts N/2 of the N messages. In ten-bit mode, N/2 of the N ten-bit messages are shifted concurrently, where each non-reconfigurable cyclic shifter shifts five of the ten bits of each ten-bit message.

Abstract: Methods and apparatus are provided for utilizing early stopping rules for non-binary turbo codes. Data can be received from a channel and decoded using a non-binary turbo code to generate extrinsic information and a posteriori information. The generated extrinsic information can be evaluated using an early stopping rule. A hard decision on a value of the received data can be made using the a posteriori information if the early stopping rule is satisfied.

Abstract: Certain embodiments of the present invention are methods for the organization of trapping-set profiles in ROM and for the searching of those profiles during (LDPC) list decoding. Profiles are ranked by dominance, i.e., by their impact on the error-floor characteristics of a decoder. More-dominant trapping-set profiles contain information about both unsatisfied check nodes (USCs) and mis-satisfied check nodes (MSCs), while less-dominant trapping-set profiles contain information about only USCs. Trapping-set profile information is organized into a number of linked, hierarchical data tables which allow for the rapid location and retrieval of most-dominant matching trapping-set profiles using a pointer-chase search.

Abstract: A memory array comprises N+1 memory elements. N memory elements store data and one or more error check bits respectively derived from the stored data. A separate N+1 memory element stores parity bits generated from the data stored in the N memory elements. These parity bits are stored in. To recover from data errors, data in each N memory element are first checked using their respective error check bits. If faulty data are detected in one of the N memory elements, an exclusive-or operation is performed involving data in the remaining N?1 memory elements and parity bits in the N+1 memory element. This recovers the faulty data in the one memory element.

Abstract: Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed.

Abstract: It is provided about a communication system mountable on a car, communication apparatus mountable on a car and a communication method mountable on a car that can perform data transmission under extensive range from a low speed communication to high speed communication, without generating data delay, data dropout and the like, caused by the data sending collision. A gateway and an ECU are connected to each other, in a one-to-one manner, via a communication line different from another communication line for another connection. When receiving a message, the gateway and the ECU reply a receipt response. When having a message to be sent toward the destination for replying at this replying time, the gateway and the ECU sends the receipt response onto which this message to be sent is added. When a message sending collision is generated, the gateway preferentially performs a message re-sending operation.

Abstract: A turbo decoding device includes a memory unit that stores data in an interleaving process performed in a process of decoding a coded signal encoded with a turbo code and an access unit that accesses the memory unit to read and write the data. The memory unit includes memory circuits and is formed as one memory space by coupling the memory circuits. Furthermore, the memory circuit functions as a first bank configuration by which a first capacity is assigned to each bank or a second bank configuration by which a second capacity is assigned to each bank in accordance with a combination of the memory circuits. Moreover, the access unit selects by which of the first bank configuration and the second bank configuration the memory unit functions in accordance with a communication method of a coded signal and accesses the memory unit in accordance with the selected bank configuration.

Abstract: A Maximum A Posteriori (MAP) decoder and a MAP decoding method are provided. The MAP decoder includes a first metric operation unit, a first bit-width control unit, a second metric operation unit, a Log Likelihood Ratio (LLR) operation unit, and a second bit-width control unit. The first metric operation unit outputs a first metric data using an input data. The first bit-width control unit controls a bit-width of the first metric data according to a modulation scheme of the input data. The second metric operation unit outputs a second metric data using the first metric data having the controlled bit-width. The LLR operation unit outputs LLR data using the second metric data. The second bit-width control unit outputs decoding data by re-controlling the bit-width of the LLR data.

Abstract: A method and system of relaying data are provided. The data is encoded into a turbo codeword by using a convolutional turbo code encoder, and the turbo codeword is transmitted from a source to a relay and a destination after puncturing by a first puncturing operation. The first punctured turbo codeword which is received in the relay is de-punctured and regenerated in a decoding operation and the regenerated turbo codeword is transmitted from the relay to the destination in punctured form after puncturing by a second puncturing operation. The punctured turbo codewords received from the source and the relay by the destination are totaled together as a totaled single turbo codeword and the totaled single turbo codeword is completely decoded to recover the data.

Abstract: An integrated circuit is interfaced with at least one dynamic random access memory (DRAM) via a memory interface. A plurality of user test options are received. The testing of the memory interface is controlled in accordance with the plurality of user test options. Test data, generated as a result of the testing of the memory interface, is stored.

Abstract: A method for rapidly characterizing the forensic contents of a digital storage device using statistical drive sampling.

Abstract: A desired coding rate is obtained by encoding source data to produce first additional data; randomizing the source data to produce randomized data; encoding the randomized data to produce second additional data; selecting a number of bits from the first and second additional data to produce first selected data and second selected data, the number of selected bits is selected based upon a data length of the source data and a desired data length of an output sequence; and multiplexing the source data with the first and second selected data. At least one of the data length of the source data and the data length of the output sequence is variable.

Abstract: Intended for an information security application, particularly in networked information systems, the present invention includes two methods and systems for verifying a current performance of a command by a controller. A first cyclic redundancy check (CRC) for the command is prestored in memory. A second CRC for the command is calculated after instructions of the command have been performed by the controller. The first CRC is compared with the second CRC. Preferably, the controller is reset if the first CRC does not match the second CRC. Also, an address of a first instruction of the command is compared with an address of a second instruction of the command to determine if there may be a discontinuity between the first and the second instructions. It is determined if the first instruction is a valid instruction from/to which an instruction sequence of the command can be redirected.

Abstract: One or more methods and systems of effectively retrieving data stored in a media of a storage device are presented. The one or more methods and systems are implemented by way of correcting and detecting errors using a multi-stage decoding process. In one embodiment, the storage device comprises a magnetic hard drive. In one embodiment, the system and method applies an encoding/decoding technique that allows error correction and detection to be performed over a number of successive decode stages or processing stages. Use of the system and method increases the maximum number of symbol errors that may be corrected in an encoded codeword, providing an improvement in data recovery.

Abstract: A single frame format is employed by a millimeter wave communication system for single-carrier and OFDM signaling. A Golay-coded sequence in the start frame delimiter (SFD) field identifies the data transmission as single carrier or OFDM. Complementary Golay codes are employed in a channel estimation field to allow a perfect estimate of the multipath channel to be made. Marker codes generated from Golay codes are inserted periodically between slots for tracking and/or for reacquiring timing, frequency, and multipath channel estimates. The length of the marker codes may be adapted relative to the multipath delay spread.