Abstract: A flash storage device comprises a plurality of channels of flash storage, a system memory, and a controller. The controller is configured to cache, in the system memory, data to be written, to partition the data into a plurality of data portions, to generate error correction information based on the plurality of data portions, to write the error correction information to a first one or more of the plurality of channels of flash storage, and to write each of the plurality of data portions to a different one of the plurality of channels of flash storage other than the first one or more thereof.

Abstract: Mechanisms for ensuring data consistency in a data store are provided. The mechanisms access a parity scrub factor f and perform a check on a data group of the data store. The check on the data group includes performing a parity check on a portion of the data group, the portion being equal to 1/f of the data group, and performing a data verify on the remainder of the data group. The performing of the check is repeated for the entire data store. An offset factor is used to select the portion of the data group for the parity check. In this case, the offset factor may be incremented when the performance of the check on the data group of the data store has been repeated for the entire data store.

Abstract: An FPGA configuration device comprises: a read operation control unit which performs control to read configuration data from a configured FPGA; and a configuration data transfer unit which transfers the configuration data read out of the FPGA to a memory.

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2t states. In a representative embodiment, the Non-ISI Meta-Viterbi detector performs ?+2t2t add, compare, and select operations.

Abstract: A decoder provided according to an aspect of the present invention determines a type of each network abstraction layer (NAL) unit, and discards a NAL unit when the size of the NAL unit is inconsistent with the size according to the determined type. According to another aspect, a decoder corrects for errors in the non-pay load portions and uses the corrected non-pay load portions to recover the original data contained in the payload portions of the data stream. In an embodiment, various global parameters (which are applicable to the data stream unless changed further in the data stream) and the values in the slice headers are examined to correct the parameters in the slice headers. According to one more aspect, an end of frame is reliably detected by using an expected number of macro-blocks in a frame and a set of logical conditions of slice header parameters.

Abstract: Methods, systems and computer readable media for controlling an instrument in communication with a host computer are provided. Operations of an instrument that must be completed on schedule are controlled via an embedded controller embedded in the instrument. A complete status packet is sent to a host computer from the embedded controller. Periodically, the embedded controller repeats the sending of a complete status packet to the host computer, wherein status values in the complete status packet are updated with each iteration of sending a complete status packet.

Abstract: A transmission apparatus includes: a CRC encoding processing unit configured to include a plurality of generating polynomials for an CRC encoding processing with each of a plurality of data of which the code lengths differ as a target, and employ the optimal generating polynomial out of the plurality of generating polynomials to perform the CRC encoding processing; and a transmission unit configured to transmit data obtained by the CRC encoding processing unit performing the CRC encoding processing.

Abstract: A data receiving apparatus includes: a header analyzing unit that analyzes a header of a frame and outputs header information; a checksum judging unit that calculates and judges a checksum of the frame; a buffer unit that stores a data portion of the frame; a reading unit that reads connection information corresponding to the header information from a second storage unit; an identifying unit that identifies a write location for the data portion based on the connection information; a data writing unit that reads data from the buffer unit and starts writing the data to the identified write location in a first storage unit before the checksum is judged; and a writing unit that, if the judgment result is “pass,” writes the connection information updated based on the header information to the second storage unit while the data writing unit is writing.

Abstract: A sound data decoding apparatus based on a waveform coding method includes a loss detector, sound data decoder, sound data analyzer, parameter modifying section and sound synthesizing section. The loss detector detects whether a loss exists in a sound data. The sound data decoder decodes the sound data to generate a first decoded sound signal. The sound data analyzer extracts a first parameter from the first decoded sound signal. The parameter modifying section modifies the first parameter based on a result of the detection of loss. The sound synthesizing section generates a first synthesized sound signal by using the modified first parameter. Thus, a deterioration of sound quality is prevented in the error compensation of sound data.

Abstract: An IP-data transmitting apparatus performs an error correction coding by classifying data into a layer indicative of the priority order of the data based on importance and vulnerability of information included in the data, and combining a plurality of data components into combination patterns. The number of the combination patterns is specified with respect to each layer with predetermined priority order.

Abstract: RLL encoding is performed to generate RLL data, including by: using a first run-length constraint and using a second run-length constraint. G is a maximum number of zeroes between two ones, I is a maximum number of zeroes between two ones in either a first subsequence or a second subsequence where the first subsequence includes odd bits associated with a DC-balanced sequence and the second subsequence includes even bits associated with the DC-balanced sequence, and S is a number of bits per symbol associated with a systematic ECC. The RLL data is encoded using the systematic ECC to obtain ECC data which includes one or more data symbols and one or more parity symbols. The data symbols and the parity symbols are interleaved.

Abstract: A method, system and article of manufacture for the storing convolution-encoded data on a redundant array of independent storage devices (RAID) is described. The convolution-encoded data comprises error correction coded data to eliminate the need for parity as used in conventional RAID data storage. The number of storage devices may vary to accommodate expansion of storage capacity and provide on demand storage.

Abstract: In a nonvolatile memory array, data is stored in multi-level cells (MLC) as upper-page data and lower-page data. Safe copies of both upper-page and lower-page data are stored in on-chip cache during programming. If a write fail occurs, data is recovered from on-chip cache. The controller does not have to maintain safe copies of data.

Abstract: A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers.

Abstract: In a transmission apparatus in a MIMO-OFDM communication system employing cyclic diversity, a cyclic delay controller sets plural delay magnitudes, different for respective antennas, in cyclic delayers for each predetermined timing. The cyclic delayers receive symbols subjected to orthogonal frequency division multiplexing, for the respective ones of plural allotted antennas. Additionally, the cyclic delayers bestow cyclic delays on the individual symbols of the respective antennas in accordance with plural set delay magnitudes. The symbols cyclically delayed are outputted from the antennas. As the delay magnitudes, a first delay magnitude at a first transmission timing and a second delay magnitude at a second transmission timing are different for one antenna, and the delay magnitudes differ in the respective antennas for one transmission timing. Thus, in a MIMO-OFDM transmission scheme, frequency diversity and time diversity are enhanced to heighten a retransmission efficiency in a data retransmission mode.

Abstract: When an error correction code (ECC) unit finds uncorrectable errors in a solid state non-volatile memory device, a process may be used in an attempt to locate and correct the errors. This process may first identify ‘low confidence’ memory cells that are likely to contain errors, and then determine what data is more likely to be correct in those cells, based on various criteria. The new data may then be checked with the ECC unit to verify that it is sufficiently correct for the ECC unit to correct any remaining errors.

Abstract: Data is processed by obtaining data and redundant information from an expected position in a channel. Soft position information associated with the data is obtained and error correction decoding is performed using the data, the redundant information, and the soft position information to obtain a decoded position and decoded data. It is determined if the decoded position matches the expected position and the decoded data is output in the event the decoded position matches the expected position.

Abstract: A method of correcting corrupted primitives transmitted between a serial advanced technology attachment (SATA) host and a SATA device includes analyzing a current state, a previously transmitted primitive, or a previously received primitive; selecting at least one candidate primitive according to at least one of the current state, the previously transmitted primitive and the previously received primitive; predicting the identity of a current primitive according to at least one candidate primitive and a received current primitive; and replacing the corrupted primitive with the predicted primitive when the predicted primitive is different from the current primitive.

Abstract: The coding apparatus, coding processing target sequence forming method and Viterbi decoding apparatus of the present invention can realize low delay processing with a minimum number of repetitive processing and suppress the degradation of the accuracy of decoding at the ends of a decoded sequence due to truncation error. In the coding apparatus mounted on the transmitting apparatus (100), a control information rearranging section (130) receives as input a control information sequence, in which a plurality of control information blocks are arranged in a predetermined order, and forms a coding processing target sequence by rearranging the order of the plurality of control information blocks to form an assembled sequence grouping control information blocks comprised of predictable bit sequences in the plurality of control information blocks, and to allocate the assembled sequence to a predetermined position in the control information sequence.

Abstract: A forward error correction (FEC) method is provided including an FEC dynamic central station and a plurality of FEC dynamic remote stations that transmit bearer data and corresponding error correction data therebetween during a plurality of time frames. The error rate of the communication channel is measured and the amount of error correction data transmitted is accordingly and dynamically adjusted, so that the minimum amount of overhead required to effectively transmit the error correction data is used.