Patents Examined by Stephen M Bradley
  • Patent number: 11127701
    Abstract: The present disclosure provides a method of manufacturing a semiconductor package. Semiconductor dies having conductive pillars are provided and are encapsulated with an insulating encapsulant. A redistribution circuit structure is formed on the insulating encapsulant and the semiconductor dies, and the redistribution circuit structure is electrically connected to the semiconductor dies. A photosensitive mask pattern having a plurality of openings is formed. A plurality of conductive vias is formed within the openings of the photosensitive mask pattern. A dielectric layer is then formed, and the conductive vias are embedded in the dielectric layer.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Jyun-Siang Peng
  • Patent number: 11127720
    Abstract: A method of repairing a light emitting device assembly includes providing a repair source substrate with an array of first light emitting diodes, providing a first carrier substrate with a temporary adhesive layer thereupon, forming a first assembly including the first carrier substrate and at least one first light emitting diode that is a subset of the array of first light emitting diodes, where the at least one first light emitting diode is attached to the first carrier substrate through a respective portion of the temporary adhesive layer and detached from the repair source substrate, providing a second carrier substrate with a temporary bonding layer thereupon, attaching the at least one first light emitting diode to the temporary bonding layer, detaching the first carrier substrate from each portion of the temporary adhesive layer, removing each portion of the temporary adhesive layer from the at least one first light emitting diode, providing a light emitting device including at least one vacancy locati
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: September 21, 2021
    Assignee: NANOSYS, INC.
    Inventors: Max Batres, Ansel Reed
  • Patent number: 11121049
    Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Siva Prakash Gurrum, Amit Sureshkumar Nangia
  • Patent number: 11121296
    Abstract: A first transparent sealing member is used in a package accommodating at least one optical element, and is attached to a mounting substrate having a mounting surface for the optical element. In the first transparent sealing member, at least one corner part among a plurality of corner parts configured by a surface facing the mounting substrate and a surface along the mounting surface of the mounting substrate has a curved shape, and punctiform minute recessed parts are formed on the surface of the curved shape. The average presence frequency of the minute recessed parts is 100,000 to 3,000,000 inclusive per 1 mm2.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: September 14, 2021
    Assignee: NGK Insulators, Ltd.
    Inventors: Yoshio Kikuchi, Hiroyuki Shibata
  • Patent number: 11120190
    Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell includes power post and ground posts in metal zero. The metal zero posts include no vias to any upper metal layers. Some variations of the standard cell have the power and ground posts routed in metal zero to a boundary edge of the standard cell. Layout rules are changed to allow this type of routing. The power and ground posts in metal zero are connected to power and ground posts in metal zero of a neighboring cell by abutment. The place-and-route tool doesn't need to perform a further routing step after placing the cells. For other variations, the power and ground posts are not routed to the boundary edge and the place-and-route tool routes power and ground connections in metal zero between the standard cell and the neighbor cell.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: September 14, 2021
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 11114627
    Abstract: The invention provides a manufacturing method for flexible display panel, comprising providing an array substrate, the array substrate comprising a semiconductor layer, dividing the flexible display panel into a pixel area and a bending area, adjacent to each other, the pixel area comprising the semiconductor layer; disposing a second groove in the bending area, and the second groove forming a step structure in the array substrate, the step structure extending from inside of the array substrate towards direction opposite to inner wall of the second groove; filling the second groove with an organic material, and the organic material filling the second groove forming a concave tapered groove with flat surface of the array substrate; fabricating a source, a drain, and source/drain wiring on the array substrate, the source and the drain being connected to the semiconductor layer, the source/drain wiring covering the tapered groove.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: September 7, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Lei Yu, Songshan Li
  • Patent number: 11114582
    Abstract: A display apparatus includes a substrate, a first electrode on the substrate, the first electrode including a first portion that has a flat upper surface and a second portion that protrudes from the first portion and has an inclined surface, a second electrode facing the first electrode in parallel on the substrate, the second electrode including a first portion that has a flat upper surface and a second portion that protrudes from the first portion and has an inclined surface, and a plurality of light-emitting devices separate from each other on the first electrode and the second electrode, the light-emitting devices each having a first end contacting the upper surface of the first portion of the first electrode and a second end contacting the upper surface of the first portion of the second electrode.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: September 7, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyunmin Cho, Daehyun Kim, Sungchul Kim, Jonghyuk Kang, Keunkyu Song, Jooyeol Lee, Hyundeok Im, Chio Cho, Hyeyong Chu, Sungjin Hong
  • Patent number: 11107838
    Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: August 31, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
  • Patent number: 11107840
    Abstract: An object of an embodiment of the present invention is to manufacture a semiconductor device with high display quality and high reliability, which includes a pixel portion and a driver circuit portion capable of high-speed operation over one substrate, using transistors having favorable electric characteristics and high reliability as switching elements. Two kinds of transistors, in each of which an oxide semiconductor layer including a crystalline region on one surface side is used as an active layer, are formed in a driver circuit portion and a pixel portion. Electric characteristics of the transistors can be selected by choosing the position of the gate electrode layer which determines the position of the channel. Thus, a semiconductor device including a driver circuit portion capable of high-speed operation and a pixel portion over one substrate can be manufactured.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: August 31, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake
  • Patent number: 11101374
    Abstract: One or more gated nanosheet diodes are disposed on a substrate and made from a nanosheet structure. A first (second) source/drain (S/D) is disposed on the substrate. The first (second) S/D has a first (second) S/D doping concentration with a first (second) S/D doping type. One or more p-n junctions form one or more respective diodes. There is a first side and a second side of each of the p-n junctions. The first (second) sides of the p-n junctions electrically and physically connect to the first (second) S/Ds and have the same type of doping, respectively. A gate stack, made of a gate dielectric layer and a gate metal, interfaces and surrounds each of the p-n junctions.
    Type: Grant
    Filed: June 13, 2020
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Karthik Balakrishnan
  • Patent number: 11094713
    Abstract: A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved conductor layers and insulating layers. The 3D memory device also includes channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes first and second source contacts separated by a support structure. The source structure also includes an adhesion layer. At least a portion of the adhesion layer is between the first and second source contacts and conductively connects the first and second source contacts.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: August 17, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Qingqing Wang, Wei Xu, Pan Huang, Ping Yan, Zongliang Huo, Wenbin Zhou
  • Patent number: 11087994
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 10, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Patent number: 11088353
    Abstract: The disclosure recites a solid-state total reflection display and a manufacture method thereof, and a display device. The solid-state total reflection display includes: a drive circuit layer, and a heating layer and a pixel function layer stacked successively on the drive circuit layer; a plurality of pixel structures in the pixel function layer are arranged in an array, and the pixel structures each includes a reflection layer, a resonant cavity layer, a phase change material layer and a transparent covering layer stacked successively; a plurality of light adjusting structures are arranged between two adjacent pixel structures among the plurality of pixel structures in a row or column direction of the array; a side of each light adjusting structure towards an ambient light-entering side of the solid-state total reflection display is in a concave shape.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 10, 2021
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yongli Jiang, Feng Lu
  • Patent number: 11081548
    Abstract: A bipolar transistor includes a collector layer, a base layer on the collector layer, and a first elongated emitter mesa on the base layer having a long side and a short side, wherein the long side is parallel with a first direction, and n separate first emitter-contact structures disposed along the first direction on the first elongated emitter mesa, where n is an integer greater than one.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: August 3, 2021
    Assignee: RichWave Technology Corp.
    Inventors: Chuan-Chen Chao, Po-Hsiang Yang
  • Patent number: 11081540
    Abstract: A display apparatus includes: a substrate having a bending area between a first area and a second area; an inorganic insulating layer arranged on the substrate, the inorganic insulating layer having an opening or a groove corresponding to the bending area; a wiring unit extending to the second area through the bending area, the wiring unit arranged on the inorganic insulating layer and at least a portion thereof overlapping the opening or the groove; and an organic material layer between the inorganic insulating layer and the wiring unit, the organic material layer configured to fill the opening or the groove, wherein the wiring unit comprises a first wire and a second wire that are adjacent to each other, and a width in which the opening or the groove overlaps the first wire is different from the width in which the opening or the groove overlaps the second wire.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: August 3, 2021
    Inventors: Mijin Yoon, Cheolsu Kim
  • Patent number: 11069535
    Abstract: Methods of depositing tungsten into high aspect ratio features using a dep-etch-dep process integrating various deposition techniques with alternating pulses of surface modification and removal during etch are provided herein.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: July 20, 2021
    Assignee: Lam Research Corporation
    Inventors: Chiukin Steven Lai, Keren Jacobs Kanarik, Samantha Tan, Anand Chandrashekar, Teh-Tien Su, Wenbing Yang, Michael Wood, Michal Danek
  • Patent number: 11069866
    Abstract: An active device substrate including a flexible substrate, an inorganic insulation layer, an organic insulation pattern, a conductive device and a peripheral wiring is provided. The flexible substrate has an active region, a peripheral region outside the active region and a bending region connected between the active region and the peripheral region. The inorganic insulation layer is disposed on the flexible substrate and has a groove disposed in the bending region. The organic insulation pattern is disposed in the groove of the inorganic insulation layer. The peripheral wiring is extended from the active region to the conductive device in the peripheral region. The peripheral wiring is disposed on the organic insulation pattern, and the organic insulation pattern is located between the peripheral wiring and the flexible substrate.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: July 20, 2021
    Assignee: Au Optronics Corporation
    Inventors: Pei-Yun Wang, Chia-Kai Chen
  • Patent number: 11056413
    Abstract: An inductor includes a conductor having a first end and a second end, wherein the first end, the second end, or both ends are configured to be mounted on a substrate and configured to receive a heat flow; and one or more magnetic cores surrounding a first portion of the conductor, the first portion of the conductor being intermediate the first end and the second end of the conductor. A second portion of the conductor not surrounded by the one or more magnetic cores is configured to transfer the heat flow from the conductor.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: July 6, 2021
    Assignee: International Business Machines Corporation
    Inventors: Xin Zhang, Todd Takken, Shurong Tian, Yuan Yao
  • Patent number: 11056582
    Abstract: A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: July 6, 2021
    Assignee: ABB Power Grids Switzerland AG
    Inventors: Jan Vobecky, Umamaheswara Vemulapati, Munaf Rahimo
  • Patent number: 11056457
    Abstract: A packaged semiconductor device includes a substrate having input/output (I/O) pads, a semiconductor die attached to the substrate and electrically connected to the substrate with bond wires. A bond-wire reinforcement structure is formed over the bond wires before the assembly is covered with a molding compound. The bond-wire reinforcement structure prevents wire sweep during molding and protects the wires from shorting with other wires. In one embodiment, the bond-wire reinforcement structure is formed with a fiberglass and liquid epoxy mixture.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 6, 2021
    Assignee: NXP USA, INC.
    Inventors: Boon Yew Low, Lan Chu Tan, Wai Yew Lo, Poh Leng Eu, Chin Teck Siong