Patents Examined by Stephen Stein
  • Patent number: 7041391
    Abstract: The present invention provides a method for forming a film of aluminum oxide in which a target containing aluminum is sputtered in a gas containing fluorine atoms. The thin film of aluminum oxide according to the present invention has little optical absorption and high refractive index in the ultraviolet and vacuum ultraviolet regions.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: May 9, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Ando, Masaaki Matsushima, Minoru Otani, Yasuyuki Suzuki, Ryuji Biro, Hidehiro Kanazawa
  • Patent number: 7037591
    Abstract: The cleaning-friendly article, such as a household kitchen appliance, which is suitable for heating food and/or directly connected with this unit, has a suitable long-lasting or permanent easily cleaned coating on its surfaces that are accessible to dirt. In order to provide this easily cleaned coating a mixture is applied to these surfaces, which contains a hydrolyzable, network-forming gel and a hydrophobic substance. The gel is preferably formed from metal oxides. such as SiO2, Al2O3, Fe2O3, In2O3, SnO2, ZrO2, B2O3 and/or TiO2. The hydrophobic substance is preferably chemically combined with the gel network. The hydrophobic substance preferably includes pre-condensed fluoroalkyl-silanes.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: May 2, 2006
    Assignee: Schott AG
    Inventors: Inka Henze, Lutz Klippe, Cora Krause, Bernd Metz, Juergen Dzick, Bernd Schultheis
  • Patent number: 7033406
    Abstract: An electrical-energy-storage unit (EESU) has as a basis material a high-permittivity composition-modified barium titanate ceramic powder. This powder is double coated with the first coating being aluminum oxide and the second coating calcium magnesium aluminosilicate glass. The components of the EESU are manufactured with the use of classical ceramic fabrication techniques which include screen printing alternating multilayers of nickel electrodes and high-permittivitiy composition-modified barium titanate powder, sintering to a closed-pore porous body, followed by hot-isostatic pressing to a void-free body. The components are configured into a multilayer array with the use of a solder-bump technique as the enabling technology so as to provide a parallel configuration of components that has the capability to store electrical energy in the range of 52 kW·h. The total weight of an EESU with this range of electrical energy storage is about 336 pounds.
    Type: Grant
    Filed: April 12, 2001
    Date of Patent: April 25, 2006
    Assignee: Eestor, inc.
    Inventors: Richard Dean Weir, Carl Walter Nelson
  • Patent number: 7029723
    Abstract: Carborane may be used as a precursor to form low dielectric constant dielectrics. The carborane material may be modified to enable it to be deposited by chemical vapor deposition.
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: April 18, 2006
    Assignee: Intel Corporation
    Inventors: Tian-An Chen, Robert Meagley, Kevin P. O'Brien, Michael D. Goodner, James Powers
  • Patent number: 7029757
    Abstract: The invention concerns a method for producing security marks on a support having a first face and a second face opposite said first face which consists in the following steps: high resolution printing with a varnish on the support first face; treating the support by electrolysis; washing and drying the support.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: April 18, 2006
    Assignee: GAJ Developpement SAS
    Inventor: Michel Levy
  • Patent number: 7026039
    Abstract: Refractory coatings comprising unstabilized zirconia, silica, and, optionally, zircon and/or mullite are disclosed herein. The unstabilized zirconia, silica, and optional zircon and/or mullite are applied as a slurry onto ceramic substrates such as silicon carbide and fired. The refractory coatings of the present invention maintained good edge definition and color when applied to ceramic substrates and subjected to temperatures over 1100° C.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: April 11, 2006
    Assignee: Saint-Gobain Ceramics & Plastics, Inc.
    Inventor: Raymond H. Bryden
  • Patent number: 7022386
    Abstract: A method for forming a glossy image comprising: using (A) a heat transfer sheet comprising a substrate, a light-heat conversion layer and an image forming layer in this order, wherein the light-heat conversion layer comprises a polyamide-imide resin, and the image forming layer comprises at least one of tabular inorganic compound particles and metal particles and a thixotropic agent, (B) a heat transfer sheet comprising a substrate, a light-heat conversion layer and an image forming layer in this order, wherein the light-heat conversion layer comprises a polyamide-imide resin, and the image forming layer comprises a transparent colorant, and (C) an image receiving sheet comprising an image receiving layer; and imagewise transferring the image forming layer of each of the heat transfer sheet (A) and the heat transfer sheet (B) to the image receiving layer by laser thermal transfer.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: April 4, 2006
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Tamotsu Suzuki
  • Patent number: 7018575
    Abstract: A method for assembly including the steps of: (a) providing a plurality of microstructure components with each of the components having a bottom with the same three dimensional shape; (b) forming a mold with at least one protuberance from a surface thereof so that the at least one protuberance has the same shape; (c) molding a moldable substrate with the mold to form a molded substrate having a surface with at least one recess having the same shape; and (d) positioning a first of the plurality of microstructure components into said at least one recess. Each of the microstructure components may be formed by a masking and etching process, with the mold being formed by the same masking and etching process. The positioning step may consist of mixing the microstructure components with a fluid to form a slurry; and depositing the slurry on the surface of the molded substrate to cause the first of the plurality of microstructure components to self-align in the recess.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: March 28, 2006
    Assignee: HRL Laboratories, LLC
    Inventors: Peter D. Brewer, Andrew T. Hunter, Luisa M. Deckard
  • Patent number: 7018728
    Abstract: A boron phosphide-based semiconductor device includes a single crystal substrate having formed thereon a boron-phosphide (BP)-based semiconductor layer containing boron and phosphorus as constituent elements, where phosphorus (P) occupying the vacant lattice point (vacancy) of boron (B) and boron occupying the vacant lattice point (vacancy) of phosphorus are present in the boron-phosphide (BP)-based semiconductor layer. The boron phosphide-based semiconductor device includes a p-type boron phosphide-based semiconductor layer in which boron occupying the vacancy of phosphorus is contained in a higher atomic concentration than phosphorus occupying the vacancy of boron and a p-type impurity of Group II element or Group I V element is added.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: March 28, 2006
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 7014916
    Abstract: The present invention relates to a transparent touch panel used for operating various electronic apparatuses. More particularly, the invention relates to a transparent touch panel where a dent is hardly generated and an electrical conductive layer is hardly damaged even when an upper surface of the transparent touch panel is continuously pressed. The transparent touch panel includes a sheet formed by sticking an upper film to a lower film via a rubber elastic layer.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: March 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Koji Tanabe
  • Patent number: 7008701
    Abstract: This invention provides an SOI substrate manufacturing method using a transfer method (bonding and separation). A separation layer (12) is formed on a silicon substrate (11). A silicon layer (13), SiGe layer (14), silicon layer (15?), and insulating layer (21) are sequentially formed on the resultant structure to prepare a first substrate (10?). This first substrate (10?) is bonded to a second substrate (30). The bonded substrate stack is separated into two parts at the separation layer (12). Next, Ge in the SiGe layer (14) is diffused into the silicon layer (13) by hydrogen annealing. With this process, a strained SOI substrate having the SiGe layer on the insulating layer (21) and a strained silicon layer on the SiGe layer is obtained.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: March 7, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuya Notsu, Nobuhiko Sato
  • Patent number: 7005193
    Abstract: A proof mass (11) for a MEMS device is provided herein. The proof mass comprises a base (13) comprising a semiconductor material, and at least one appendage (15) adjoined to said base by way of a stem (21). The appendage (15) comprises a metal (17) or other such material that may be disposed on a semiconductor material (19). The metal increases the total mass of the proof mass (11) as compared to a proof mass of similar dimensions made solely from semiconductor materials, without increasing the size of the proof mass. At the same time, the attachment of the appendage (15) by way of a stem (21) prevents stresses arising from CTE differentials in the appendage from being transmitted to the base, where they could contribute to temperature errors.
    Type: Grant
    Filed: April 29, 2003
    Date of Patent: February 28, 2006
    Assignee: Motorola, Inc.
    Inventors: Andrew C. McNeil, Gary Li, Gary J. O'Brien
  • Patent number: 7001641
    Abstract: Seed layer treatment to remove impurities in the seed layer that might lead to the formation of voids in interconnect circuit features. In one embodiment, the seed layer is heated in a reducing environment. In another embodiment, the seed layer is washed with a surfactant that is compatible with a surfactant used when forming the remainder of the circuit feature on the seed layer. Yet another embodiment combines both techniques.
    Type: Grant
    Filed: September 23, 2002
    Date of Patent: February 21, 2006
    Assignee: Intel Corporation
    Inventors: Valery M. Dubin, Christopher D. Thomas, Vinay B. Chikarmane
  • Patent number: 7001656
    Abstract: The invention relates to a rigid multilayer material for thermal insulation, in particular in a vacuum, the material comprising at least one insulating plate of honeycomb material sandwiched between two aluminum- or gold-coated skins of low emissivity. In order to optimize thermal insulation, the diameter of the cells is at least twice their height. The multilayer material may have as many layers as needed. The cells of adjacent layers may be offset in order to further minimize paths for heat conduction through the structure. Holes may be pierced in the side walls of the cells in order to allow them to empty out when the material is put into a vacuum. The invention also provides a method of making such a material.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: February 21, 2006
    Assignee: Alcatel
    Inventors: Michel Maignan, Thierry Youssefi, Bertrand Brevart
  • Patent number: 6994903
    Abstract: A hybrid substrate, i.e., a substrate fabricated from different materials, and method for fabricating the same are presented. The hybrid substrate is configured for fabricating more than two different devices thereon, has a high thermal conductivity, and is configured for patterning interconnects thereon for interconnecting the different devices fabricated on the hybrid substrate.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: February 7, 2006
    Assignee: International Business Machines Corp.
    Inventors: Louis L. Hsu, Li-Kong Wang
  • Patent number: 6989179
    Abstract: A synthetic grass sport surface (10) suited for use in a baseball field includes an infill layer (16) of particulate material evenly spread among rows of ribbons (14) extending upwardly from a backing mat (12). The infill layer (16) includes a top covering sub-layer (26) of non-marking material, such as recycled rubber used in the manufacture of soles for running shoes. A checkered pattern of alternating color tones is formed on the synthetic grass surface (16) for improving the natural appearance thereof. The synthetic grass surface also includes a synthetic grass warning track (34) having different tangible properties to alert a player stepping thereon that he is approaching an obstacle.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: January 24, 2006
    Assignee: Fieldturf (IP) Inc.
    Inventors: Jean Prevost, John Gilman
  • Patent number: 6986955
    Abstract: Epitaxial and reduced grain boundary materials are deposited on substrates for use in electronic and optical applications. A specific material disclosed is epitaxial barium strontium titanate (14) deposited on the C-plane of sapphire (12).
    Type: Grant
    Filed: August 2, 2001
    Date of Patent: January 17, 2006
    Assignee: nGimat Co.
    Inventors: Jerome Schmitt, George Guang-Ji Cui, Henry A. Luten, III, Fang Yang, Fe Alma Gladden, Scott Flanagan, Yongdong Jiang, Andrew Tye Hunt
  • Patent number: 6982125
    Abstract: An electrostatic chuck is provided which includes a ceramic body comprising aluminum nitride (AlN), and at least one electrode in the ceramic body. According to a particular feature of this embodiment, the aluminum nitride has a resistivity ratio ?10V/?500V less than about 5. In this regard, ?10V represents the resistivity of the electrostatic chuck at 10 applied volts while ?500V represents the resistivity of the AlN material at 500 applied volts.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: January 3, 2006
    Assignee: Saint-Gobain Ceramics & Plastics, Inc.
    Inventors: Brian C. LaCourse, Morteza Zandi, Ara Vartabedian
  • Patent number: 6979489
    Abstract: In the present invention, there are provided self-assembled ZnO nanotips grown on relatively low temperatures on various substrates by metalorganic chemical vapor deposition (MOCVD). The ZnO nanotips are made at relatively low temperatures, giving ZnO a unique advantage over other wide bandgap semiconductors such as GaN and SiC. The nanotips have controlled uniform size, distribution and orientation. These ZnO nanotips are of single crystal quality, show n-type conductivity and have good optical properties. Selective growth of ZnO nanotips also has been realized on patterned (100) silicon on r-sapphire (SOS), and amorphous SiO2 on r-sapphire substrates. Self-assembled ZnO nanotips can also be selectively grown on patterned layers or islands made of a semiconductor, an insulator or a metal deposited on R-plane (01{overscore (1)}2) Al2O3 substrates as long as the ZnO grows in a columnar stucture along the c-axis [0001] of ZnO on these materials.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: December 27, 2005
    Assignee: Rutgers, The State University of New Jersey
    Inventors: Yicheng Lu, Sriram Muthukumar, Nuri William Emanetoglu
  • Patent number: RE38959
    Abstract: An aluminosilicate glass having a composition consisting essentially of, as calculated in weight percent on an oxide basis, of 58-70% SiO2, 12-22% Al2O3, 3-15% B2O3, 2-12% CaO, 0-3% SrO, 0-3% BaO, 0-8% MgO, 10-25% MCSB (i.e., MgO+CaO+SrO+BaO), and SrO and BaO in combination being less than 3%.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: January 31, 2006
    Assignee: Corning Incorporated
    Inventor: Jeffrey T. Kohli