Patents Examined by Stephen Stein
  • Patent number: 6917776
    Abstract: A discharge wire usable in an electrification device includes a tungsten wire subjected to mirror finish processing and an oxidized layer formed by heating the surface of the tungsten wire at a temperature in the range 400 to 600° C., wherein the film has a thickness in the range of 0.01 to 0.3 ?m.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: July 12, 2005
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tsuyoshi Kunishi, Nobuhiro Hayashi, Toru Kabashima
  • Patent number: 6916522
    Abstract: A main object of the present invention is to provide a charge-giving body capable of forming a pattern having a minute structure on a surface of a semiconductor by a simple process; and a minute pattern-formed body. The present invention is a charge-giving body, comprising a defected region in which defect is introduced into a crystal structure in a crystalline semiconductor surface, charge being given from the defected region.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: July 12, 2005
    Assignee: Waseda University
    Inventor: Takayuki Homma
  • Patent number: 6916560
    Abstract: The invention relates to a silicone nitride based substrate for semi-conductor components, said substrate containing silicon nitride (Si3N4), silicon carbide (SIC) and silicon oxynitride(Si2N2O) as crystalline phases. The silicon phase content is less or equal to 5%, the shrinkage during production is less than 5% and the open porosity of the substrate is less than 15% vol. %. The invention also relates to a method for the production and use of said substrate as an element of semi-conductor components, particularly thin film solar cells, and semi-conductor components which contain said substrate.
    Type: Grant
    Filed: November 22, 2001
    Date of Patent: July 12, 2005
    Assignee: H. C. Starck Ceramics GmbH & Co. KG
    Inventors: Gerhard Wötting, Peter Woditsch, Christian Hässler, Gunther Stollwerck
  • Patent number: 6916525
    Abstract: A method of using films having optimized optical properties for chemical mechanical polishing (CMP) endpoint detection. Specifically, one embodiment of the present invention includes a method for improving chemical mechanical polishing endpoint detection. The method comprises the step of depositing a dielectric layer over a reflectance stop layer. The reflectance stop layer is disposed above a component that is disposed on a semiconductor wafer. During a determination of the thickness of the dielectric layer using a reflected signal of light, the reflectance stop layer substantially reduces any light from reflecting off of the component. Therefore, the present invention provides a method and system that provides more accurate endpoint detection during a CMP process of semiconductor wafers. As a result of the present invention, an operator of a CMP machine knows precisely when to stop a CMP process of a semiconductor wafer.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: July 12, 2005
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Subhas Bothra, Milind G. Weling
  • Patent number: 6905771
    Abstract: A silicon wafer is doped with boron and germanium in a range that satisfies a relational expression defined by: ?0.8×10?3?4.64×10?24×[Ge]?2.69×10?23×[B]?1.5×10?3. This can reduce the miss-fit dislocation which might be induced when an epitaxial layer is grown over the silicon wafer that has been added with boron in high concentration. It is to be noted that in the above relational expression, the [B] denotes a boron concentration, while the [Ge] denotes a germanium concentration and a concentration unit is indicated by atoms/cm3.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: June 14, 2005
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Toshiaki Ono, Tadami Tanaka, Masataka Hourai
  • Patent number: 6896981
    Abstract: A transparent conductive film has a polymer film 4 and a transparent conductive layer 5 formed on the polymer film 4. The transparent conductive layer includes indium oxide, a zinc oxide system and a tin oxide system. A covering layer 9, made of material different from that of the transparent conductive layer 5, is formed on the transparent conductive layer 5. A touch panel is provided with the transparent conductive film as its upper electrode 6A or lower electrode. The surface of the transparent conductive layer is covered with the covering layer, so that physical or chemical stresses generated during the input to the touch panel do not affect transparent conductive layer directly, thus preventing damages and delamination of the transparent conductive layer. Furthermore, the covering layer formed on the transparent conductive layer improves the strength of the transparent conductive film, thereby enhancing a resistance to wear.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: May 24, 2005
    Assignee: Bridgestone Corporation
    Inventors: Yoshinori Iwabuchi, Taichi Kobayashi, Shingo Ohno, Yukihiro Kusano, Masato Yoshikawa
  • Patent number: 6896969
    Abstract: A metal oxide layer may made more highly oxidized by exposing the layer to sulfur trioxide. The leakage current of the layer may thereby be decreased, providing a capacitor containing such a layer with improved performance properties. The capacitor may be incorporated into a dynamic random access memory cell or other structure useful in the semiconductor or other industry.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: May 24, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Alan R. Reinberg
  • Patent number: 6896976
    Abstract: A semiconductor device is disclosed containing a semiconductor die having a trimetal electrode soldered to a substrate by a Sn—Sb solder.
    Type: Grant
    Filed: April 9, 2003
    Date of Patent: May 24, 2005
    Assignee: International Rectifier Corporation
    Inventor: Chuan Cheah
  • Patent number: 6893728
    Abstract: The present invention provides a low temperature fired porcelain comprising crystalline phases including sanbornite, celsian and ?-cristobalite phases when measured by a high power X-ray diffractometer. The ratio of the peak intensity of (101) plane of ?-cristobalite phase to the peak intensity of (101) plane of sanbornite phase is not higher than 5%. The porcelain is of a low temperature fired porcelain of silica-alumina-barium oxide system with cristobalite phase precipitated, in which the incidence of cracks in the porcelain may be reduced.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: May 17, 2005
    Assignee: NGK Insulators, Ltd.
    Inventor: Takeshi Oobuchi
  • Patent number: 6893751
    Abstract: A composite product comprising a substrate layer and one or more functional layers applied thereto. The slurry is applied to the substrate layer to form a functional layer and the functional layer dewatered through the substrate layer. The functional layers can be repeated to build up a laminated composite product. Functional additives may be included in each layer to provide desired properties to that layer and indeed to the subsequent composite product.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: May 17, 2005
    Assignee: James Hardie Research Pty Limited
    Inventors: Basil Naji, John Sydney Cottier, Robert Lyons
  • Patent number: 6887576
    Abstract: An object of the present invention is to provide a quartz glass body, especially a quartz glass jig for plasma reaction in producing semiconductors having excellent resistance against plasma corrosion, particularly, excellent corrosion resistance against F-based gaseous plasma; and a method for producing the same. A body made of quartz glass containing a metallic element and having an improved resistance against plasma corrosion is provided that contains bubbles and crystalline phase at an amount expressed by projected area of less than 100 mm2 per 100 cm3.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: May 3, 2005
    Assignees: Herseus Quarzglas GmbH & Co. KG, Shin-Etsu Quartz Products Co., Ltd.
    Inventors: Tatsuhiro Sato, Nobumasa Yoshida, Akira Fujinoki, Kyoichi Inaki, Tomoyuki Shirai
  • Patent number: 6887579
    Abstract: A metal oxide layer may made more highly oxidized by exposing the layer to sulfur trioxide. The leakage current of the layer may thereby be decreased, providing a capacitor containing such a layer with improved performance properties. The capacitor may be incorporated into a dynamic random access memory cell or other structure useful in the semiconductor or other industry.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: May 3, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Alan R. Reinberg
  • Patent number: 6881487
    Abstract: A coated article is provided with a coating or layer system that includes at least one layer including zirconium (Zr) and/or zirconium nitride (ZrNx) sandwiched between at least a pair of dielectric layers. In certain example embodiments, the coating or layer system has good corrosion resistance, good mechanical performance such as scratch resistance, and/or good color stability (i.e., a low ?E* value(s)) upon heat treatment (HT).
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: April 19, 2005
    Assignee: Guardian Industries Corp.
    Inventor: Yuping Lin
  • Patent number: 6878451
    Abstract: There are provided silicon single crystal, silicon wafer, and epitaxial wafer having a sufficient gettering effect suitable for a large-scale integrated device. The silicon single crystal which is suitable for an epitaxial wafer is grown with nitrogen doping at a concentration of 1×1013 atoms/cm3 or more, or with nitrogen doping at a concentration of 1×1012 atoms/cm3 and carbon doping at a concentration of 0.1×1016-5×1016 atoms/cm3 and/or boron doping at a concentration of 1×1017 atoms/cm3 or more. The silicon wafer is produced by slicing from the silicon single crystal, and an epitaxial layer is grown on a surface of the silicon wafer to produce the epitaxial wafer. The present invention provides an epitaxial wafer for a large-scale integrated device having no defects in a device-active region and having an excellent gettering effect without performance of an extrinsic or intrinsic gettering treatment, which is a factor for increasing the number of production steps and production costs.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: April 12, 2005
    Assignee: Sumitomo Mitsubishi Silicon Corporation
    Inventors: Eiichi Asayama, Masataka Horai, Hiroki Murakami, Takayuki Kubo
  • Patent number: 6878463
    Abstract: A low cost, durable mask for use in structuring anodically bondable glass materials and other structurable glass materials.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: April 12, 2005
    Assignee: Honeywell International, Inc.
    Inventor: Amy V. Skrobis
  • Patent number: 6875319
    Abstract: The invention concerns a method from cathode spray deposition of a coating with photocatalytic properties comprising titanium oxide at least partly crystallised in anastatic form on a transparent or semi-transparent support substrate, such as glass, vitroceramic, plastic. The substrate is sprayed under a pressure of at least 2 Pa. The invention also concerns the resulting coated substrate, wherein said substrate constitutes the top layer of a series of thin antiglare layers.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: April 5, 2005
    Assignee: Saint-Gobain Glass France
    Inventors: Nicolas Nadaud, Xavier Talpaert, Veronique Rondeau
  • Patent number: 6872479
    Abstract: The invention is directed to a coated metal fluoride crystals that are resistant to laser-induced damage by a below 250 nm UV laser beam; methods of making such coated crystals, and the use of such coated crystals. The method includes the steps of providing an uncoated metal fluoride crystal of general formula MF2, where M is beryllium, magnesium, calcium, strontium and barium, and mixtures thereof, and coating the uncoated metal fluoride crystal with a coating of a selected material to thereby form a coated metal material resistant to laser induced damage. Preferred coating materials include MgF2, MgF2 doped fused silica and fluorine doped fused silica.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: March 29, 2005
    Assignee: Corning Incorporated
    Inventors: Robert L. Maier, Robert W. Sparrow, Paul M. Then
  • Patent number: 6872455
    Abstract: A method for enhancing the equilibrium solubility of boron ad indium in silicon. The method involves first-principles quantum mechanical calculations to determine the temperature dependence of the equilibrium solubility of two important p-type dopants in silicon, namely boron and indium, under various strain conditions. The equilibrium thermodynamic solubility of size-mismatched impurities, such as boron and indium in silicon, can be raised significantly if the silicon substrate is strained appropriately. For example, for boron, a 1% compressive strain raises the equilibrium solubility by 100% at 1100° C.; and for indium, a 1% tensile strain at 1100° C., corresponds to an enhancement of the solubility by 200%.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: March 29, 2005
    Assignee: The Regents of the University of California
    Inventors: Babak Sadigh, Thomas J. Lenosky, Tomas Diaz de la Rubia, Martin Giles, Maria-Jose Caturla, Vidvuds Ozolins, Mark Asta, Silva Theiss, Majeed Foad, Andrew Quong
  • Patent number: 6869702
    Abstract: A substrate for epitaxial growth allowing formation of an Al-containing group III nitride film having high crystal quality is provided. A nitride film containing at least Al is formed on a 6H—SiC base by CVD at a temperature of at least 1100° C., for example. The substrate for epitaxial growth allowing formation of an Al-containing group III nitride film having high crystal quality is obtained by setting the dislocation density of the nitride film to not more than 1×1011/cm2, the full width at half maximum of an X-ray rocking curve for (002) plane to not more than 200 seconds and the full width at the half maximum of the X-ray rocking curve for (102) plane to not more than 1500 seconds.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: March 22, 2005
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomohiko Shibata, Shigeaki Sumiya, Keiichiro Asai, Mitsuhiro Tanaka
  • Patent number: 6866943
    Abstract: A bond pad structure formed over a predetermined area of an IC substrate comprising quickly and easily removable redundancy and passivation layers upon lithography and plasma etching in a plasma containing Cl2, the bond structure comprises: a liner or lower metal layer formed on a predetermined area of the IC substrate; an aluminum-based metal layer formed on the liner layer as the last metal layer for bond purposes; a tungsten based redundancy layer formed on top of the aluminum-based last metal layer; and a passivation layer formed over the IC substrate and on the tungsten based redundancy layer.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: March 15, 2005
    Assignee: Infineon Technologies AG
    Inventors: Gerald Friese, Werner K. Robl, Hans-Joachim Barth, Axel Brintzinger