Patents Examined by Stephen W. Smoot
  • Patent number: 10714466
    Abstract: A layout pattern for magnetoresistive random access memory (MRAM) includes: a first magnetic tunneling junction (MTJ) pattern on a substrate; a second MTJ pattern adjacent to the first MTJ pattern; and a first metal interconnection pattern between the first MTJ pattern and the second MTJ pattern, wherein the first MTJ pattern, the first metal interconnection pattern, and the second MTJ pattern comprise a staggered arrangement.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Liang Chu, Chih-Hsien Tang, Yu-Ruei Chen, Ya-Huei Tsai, Rai-Min Huang, Chueh-Fei Tai
  • Patent number: 10714570
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure present on a channel region portion of the plurality of suspended nanowires. The gate structure has a uniform length extending from an upper surface of the gate structure to the base of the gate structure. The semiconductor device further includes a dielectric spacer having a uniform composition in direct contact with the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10714678
    Abstract: The methods of manufacturing an MRAM device and MRAM devices are provided. The methods may include forming a first electrode on an upper surface of a substrate, forming a first magnetic layer on the first electrode, forming a tunnel barrier structure on the first magnetic layer, forming a second magnetic layer on the tunnel barrier structure, and forming a second electrode on the second magnetic layer. The tunnel barrier structure may include a first tunnel barrier layer and a second tunnel barrier layer that are sequentially stacked on the first magnetic layer and may have different resistivity distributions from each other along a horizontal direction that may be parallel to the upper surface of the substrate.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Sung Park, Woo-Jin Kim, Jeong-Heon Park, Se-Chung Oh, Joon-Myoung Lee, Hyun Cho
  • Patent number: 10714344
    Abstract: Embodiments described herein relate generally to methods for forming a mask for patterning a feature in semiconductor processing. In an embodiment, a dielectric layer is formed over a substrate. A mask is formed over the dielectric layer. Forming the mask includes depositing a first layer over the dielectric layer; implanting in a first implant process a dopant species through a patterned material and into the first layer at a first energy; after implanting in the first implant process, implanting in a second implant process the dopant species through the patterned material and into the first layer at a second energy greater than the first energy; and forming mask portions of the mask comprising selectively removing portions of the first layer that are not implanted with the dopant species.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tien-Shun Chang, Chun-Feng Nieh, Huicheng Chang
  • Patent number: 10707319
    Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Mark L. Doczy, Suman Datta, Justin K. Brask, Matthew V. Metz
  • Patent number: 10700268
    Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes (a) etching through at least a portion of a thickness of the surface region to create a first set of exposed areas in the form of multiple strips extending in a first direction, and (b) etching through at least a portion of a thickness of the surface region to create a second set of exposed areas in the form of multiple strips extending in a second direction. The first set of exposed areas and the second set of exposed areas may have multiple areas that overlap. The method may also include, (c) after the etching in (a) and (b), etching through at least a portion of the thickness of the magnetoresistive stack through the first set and second set of exposed areas.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: June 30, 2020
    Assignee: Everspin Technologies, Inc.
    Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Sarin A. Deshpande
  • Patent number: 10700129
    Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a conductive horizontal electrode, an opening extending through the horizontal electrode, a filament region positioned within the opening and communicatively coupled to a sidewall of the horizontal electrode, and a conductive vertical electrode positioned within the opening and communicatively coupled to the filament region. The vertical electrode includes a first conductive alloy material. Oxygen vacancy formation in the filament region is controlled by the first conductive alloy material of the vertical electrode. A room temperature resistivity of the first conductive alloy material is below about 5×10?8 ohm meters and controlled by at least one of the metals that form the first conductive alloy material.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 30, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Choonghyun Lee
  • Patent number: 10700110
    Abstract: A fan-out sensor package includes: a substrate in which a through-hole is formed and portions of a wiring layer are exposed from an insulating layer; an image sensor having an active surface having a sensing region disposed below the through-hole of the substrate and connection pads disposed in the vicinity of the sensing region; an optical member disposed on the active surface of the image sensor; a dam member disposed in the vicinity of the sensing region; and an encapsulant encapsulating the substrate and the image sensor, wherein the third wiring layer and the connection pads are electrically connected to each other by connection members.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Hyun Lim, Yoon Seok Seo, Kyung Moon Jung, Eun Jin Kim
  • Patent number: 10692897
    Abstract: A flexible display is provided, including a substrate; a plurality of thin film transistors spacedly arranged apart from each other and disposed along a first direction on the substrate; a plurality of spacers spacedly arranged apart from each other and disposed along the first direction on the substrate, where each of the spacers fills an interval between two adjacent thin film transistors; and at least one wire configured to electrically connect the two adjacent thin film transistors, where the at least one wire is disposed in a corresponding spacer. The present disclosure can effectively prevent wire breakage between thin film transistors by using curved wires to electrically connect adjacent thin film transistors along the first direction in the substrate.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: June 23, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Fuyang Zhang
  • Patent number: 10693005
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Patent number: 10685834
    Abstract: A method for forming a forming a silicon germanium tin (SiGeSn) layer is disclosed. The method may include, providing a substrate within a reaction chamber, exposing the substrate to a pre-deposition precursor pulse, which comprises tin tetrachloride (SnCl4), exposing the substrate to a deposition precursor gas mixture comprising a hydrogenated silicon source, germane (GeH4), and tin tetrachloride (SnCl4), and depositing the silicon germanium tin (SiGeSn) layer over a surface of the substrate. Semiconductor device structures including a silicon germanium tin (SiGeSn) layer formed by the methods of the disclosure are also provided.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: June 16, 2020
    Assignee: ASM IP Holdings B.V.
    Inventors: Nupur Bhargava, Joe Margetis, John Tolle
  • Patent number: 10680062
    Abstract: A gate-all-around field effect transistor (GAA FET) includes an InAs nano-wire as a channel layer, a gate dielectric layer wrapping the InAs nano-wire, and a gate electrode metal layer formed on the gate dielectric layer. The InAs nano-wire has first to fourth major surfaces three convex-rounded corner surfaces and one concave-rounded corner surface.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mark Van Dal, Gerben Doornbos, Matthias Passlack, Martin Christopher Holland
  • Patent number: 10680098
    Abstract: An LDMOS device in FinFET technology is disclosed. In one aspect, the device includes a first region substantially surrounded by a second region of different polarity. The device further includes a first fin in the first region, extending into the second region, the first fin including a doped source region connected with a first local interconnect. The device further includes a second fin in the second region, including a doped drain region connected with a second local interconnect. The device further includes a third fin parallel with the first and second fins including a doped drain region connected with the second local interconnect. The device further includes a gate over the first fin at the border between the first and second regions. A first current path runs over the first and second fins. A second current path runs over and perpendicular to the first fin towards the third fin.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 9, 2020
    Assignee: IMEC vzw
    Inventors: Shih-Hung Chen, Dimitri Linten, Geert Hellings
  • Patent number: 10672809
    Abstract: The present disclosure relates to a solid-state imaging apparatus that is configured by laminating a first structure body, at which a pixel array unit in which pixels for performing photoelectric conversion are two-dimensionally aligned is formed, and a second structure body, at which an output circuit unit for outputting a pixel signal outputted from the pixels to the outside of the apparatus is formed. The output circuit unit, a through via which penetrates a semiconductor substrate constituting a part of the second structure body, and a signal output external terminal connected to the outside of the apparatus are arranged under the pixel array unit of the first structure body, the output circuit unit is connected to the signal output external terminal via the through via, and the outermost surface of the apparatus is a resin layer formed on an upper layer of an on-chip lens of the pixel array unit.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: June 2, 2020
    Assignee: Sony Corporation
    Inventors: Harumi Tanaka, Yoshiaki Masuda, Shinji Miyazawa, Minoru Ishida
  • Patent number: 10672724
    Abstract: The present technology relates to a semiconductor device, a manufacturing method of a semiconductor device, an integrated substrate, and an electronic device capable of improving moisture resistance of the semiconductor device. The semiconductor device includes a semiconductor chip and a protective member which is a transparent member having moisture resistance and covers at least one of a first surface perpendicular to a side surface of the semiconductor chip or a second surface opposite to the first surface and the side surfaces. The electronic device includes the semiconductor device and the signal processing unit. The present technology is applied to, for example, an imaging element and an electronic device including an imaging element.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: June 2, 2020
    Assignee: SONY CORPORATION
    Inventor: Yuichi Yamamoto
  • Patent number: 10664554
    Abstract: A measurement apparatus is used in cooperation with another equivalent measurement apparatus. Each measurement apparatus includes a change amount calculator for calculating a change amount of measured values, an average value generator for generating a first internal average value based on the change amount, and a communication unit for receiving a second internal average value that was generated by at least one other measurement apparatus. The average value generator generates a third internal average value, using a computation result based on at least the first and second internal average values.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: May 26, 2020
    Assignee: DAIHEN Corporation
    Inventors: Akihiro Ohori, Nobuyuki Hattori
  • Patent number: 10665606
    Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokcheon Baek, Geunwon Lim, Hwan Lee
  • Patent number: 10665781
    Abstract: An embodiment includes a programmable metallization cell (PMC) memory comprising: a top electrode and a bottom electrode; a metal layer between the top and bottom electrodes; and a solid electrolyte (SE) layer between the metal layer and the bottom electrode; wherein (a) the metal layer includes an alloy of first and second metals, and (b) metal ions from the first metal form a conductive path in the SE layer when the top electrode is positively biased and disband the conductive path when the top electrode is negatively biased. Other embodiments are described herein.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 26, 2020
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Jeffery D. Bielefeld, James S. Clarke, Ravi Pillarisetty, Uday Shah
  • Patent number: 10658585
    Abstract: Methods and devices are provided for fabricating a resistive random-access array having dedicated electroforming contacts. A lower conductive line is formed on an interlayer dielectric layer. A lower electrode is formed on the lower conductive line. An isolation layer is formed having an upper surface which is coplanar with an upper surface of the lower electrode. A stack structure including a metal-oxide layer and upper electrode is formed on the lower electrode. Insulating spacers are formed on sidewalls of the stack structure. The lower electrode, and stack structure form a resistive memory cell, wherein a footprint of the lower electrode is greater than that of the upper electrode. An upper conductive line contacts the upper electrode, and is arranged orthogonal to the lower conductive line. A dedicated electroforming contact contacts an extended portion of the lower electrode which extends past a cross-point of the upper and lower conductive lines.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Lawrence A. Clevenger, Chih-Chao Yang, Benjamin D. Briggs
  • Patent number: 10658456
    Abstract: The present disclosure provides a method of manufacturing a Schottky diode. The method includes: providing a substrate; forming a first well region in the substrate; defining a first portion and a second portion on a surface of the first well region and performing a first ion implantation on the first portion while keeping the second portion from being implanted; forming a first doped region by heating the substrate to cause dopant diffusion between the first portion and the second portion; and forming a metal-containing layer on the first doped region to obtain a Schottky barrier interface.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wen-Shun Lo, Yu-Chi Chang, Felix Ying-Kit Tsui