Patents Examined by Steven H. Loke
  • Patent number: 11152677
    Abstract: Integration of self-biased magnetic circulators with microwave devices is disclosed herein. In microwave and other high-frequency radio frequency (RF) applications, a magnetic circulator can be implemented with a smaller permanent magnet. Aspects disclosed herein include a process flow for producing a self-biased circulator in an integrated circuit chip. In this regard, a magnetic circulator junction can be fabricated on an active layer of a semiconductor wafer. A deep pocket or cavity is formed in an insulating substrate under the active layer. This cavity is then filled with a ferromagnetic material such that the circulator junction is self-biased within the integrated circuit chip, eliminating the need for an external magnet. The self-biased circulator provides high isolation between ports in a smaller integrated circuit.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 19, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Yongjie Cui, Xing Gu, Andrew Arthur Ketterson, Cathy Lee, Xing Chen
  • Patent number: 11152508
    Abstract: A semiconductor device including a 2D material layer disposed between a gate electrode and a substrate and a method of forming the same are disclosed. In an embodiment, a device includes a ferroelectric dielectric layer disposed over and in contact with a semiconductor substrate, the ferroelectric dielectric layer including a 2D material; a gate electrode disposed over the ferroelectric dielectric layer; and source/drain regions disposed on opposite sides of the gate electrode.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi On Chui, Sai-Hooi Yeong, Syun-Ming Jang, Min Cao
  • Patent number: 11152466
    Abstract: A semiconductor device includes a semiconductor body; a first electrode on the semiconductor body; control electrodes provided in the semiconductor body along the surface thereof; and first films electrically insulating the control electrodes from the semiconductor body. The semiconductor body includes first, third, sixth layers of a first conductivity type, and second, fourth, fifth layers of a second conductivity type. The second to sixth layers are provided between the first electrode and the first layer. The second and third layers are positioned between two adjacent control electrodes. The fourth to sixth layers are positioned between other two adjacent control electrodes. The sixth layer positioned between the fourth layer and the fifth layer. The sixth layer includes a major portion and a boundary portion between the major portion and one of the first films. An impurity concentration in the boundary portion is lower than that in the major portion.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: October 19, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa
  • Patent number: 11152454
    Abstract: In an embodiment, a semiconductor device includes a resistor that overlies a doped region of the semiconductor device. The resistor is formed into a pattern of a polygon spiral. An embodiment of the pattern of the resistor includes sides and corners. The material of the sides has a low resistivity and the material of the corners has a higher resistivity.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 19, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Arash Elhami Khorasani, Mark Griswold
  • Patent number: 11145778
    Abstract: An optical system may include a substrate and a plurality of silicon photomultipliers (SiPMs) monolithically integrated with the substrate. Each SiPM may include a plurality of single photon avalanche diodes (SPADs). The optical system also includes an aperture array having a plurality of apertures. The plurality of SiPMs and the aperture array are aligned so as to define a plurality of receiver channels. Each receiver channel includes a respective SiPM of the plurality of SiPMs optically coupled to a respective aperture of the plurality of apertures.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 12, 2021
    Assignee: Waymo LLC
    Inventors: Caner Onal, Pierre-Yves Droz, Nirav Dharia
  • Patent number: 11131647
    Abstract: A method for fabricating a semiconductor device including an ion-sensitive field-effect transistor (ISFET) with enhanced sensitivity includes forming a sawtooth microwell within a base structure formed on a semiconductor chip corresponding to an ISFET, including using a sawtooth mask to etch through the base structure to expose the semiconductor chip, removing the sawtooth mask, and forming a sawtooth macrowell from the sawtooth microwell.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 28, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, Kangguo Cheng, Juntao Li, Ruilong Xie
  • Patent number: 11133183
    Abstract: The disclosure describes a tunneling field effect transistor having an overlapping structure between the source and drain regions providing a greater tunneling area. The source or drain region may be a doped region in a semi-conductive substrate. The other source or drain region may be formed by epitaxial deposition over the doped region. The gate is formed over the epitaxial region where the doped and epitaxial regions overlap. The doped region may be formed in a fin structure with the epitaxial region and gate being formed on the top and sides of the fin.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: September 28, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Chiao Tung University
    Inventors: Steve S. Chung, E. Ray Hsieh, Kuan-Yu Chang
  • Patent number: 11127445
    Abstract: According to one embodiment, a magnetic device includes a magnetic tunnel junction element, the magnetic tunnel junction element comprising: a first structure having ferromagnetism; a second structure having ferromagnetism; and a first nonmagnet provided between the first structure and the second structure; wherein: the first structure and the second structure are antiferromagnetically coupled via the first nonmagnet; and the first structure includes a first ferromagnetic nitride.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 21, 2021
    Assignees: TOSHIBA MEMORY CORPORATION, SK HYNIX INC.
    Inventors: Young Min Eeh, Taeyoung Lee, Kazuya Sawada, Eiji Kitagawa, Taiga Isoda, Tadaaki Oikawa, Kenichi Yoshino
  • Patent number: 11121188
    Abstract: An organic light-emitting display apparatus includes a display layer including a first non-light-emitting area in which a pixel-defining layer surrounding a light-emitting area is arranged, and a second non-light-emitting area further including a spacer on the pixel-defining layer; a light shield layer including a first black matrix and a second matrix covering the first non-light-emitting area and the second non-light-emitting area, respectively, and having different dielectric constants; and a touchscreen electrode including a touch electrode on a position corresponding to the first black matrix and the second matrix.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kangmoon Jo, Dongwoo Kim, Youngmin Kim, Sungjae Moon, Kisoo Park, Junhyun Park, Ansu Lee
  • Patent number: 11101241
    Abstract: The semiconductor device includes, on the cooling substrate, first main terminal, second main terminal, third main terminal, and fourth main terminal, each having a polygonal-shape. The first external-connection face on upper surface of the first main terminal is connected to positive electrode, and the fourth external-connection face on upper surface of the fourth main terminal is connected to negative electrode. First semiconductor element electrically connected between side surface of the first main terminal and side surface of the second main terminal, and second semiconductor element electrically connected between side surface of the third main terminal and side surface of the fourth main terminal are provided. The second main terminal and the third main terminal are disposed adjacent to each other while being separated, and the first main terminal and the fourth main terminal are disposed adjacent to each other while being separated.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: August 24, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hideyo Nakamura
  • Patent number: 11101381
    Abstract: A structure of a high voltage transistor includes a substrate. A gate insulating layer is disposed on the substrate. A shallow trench isolation structure is formed in the substrate adjacent to the gate insulating layer. The shallow trench isolation structure includes a first sidewall and a second sidewall. A top portion of the first sidewall merges with a side region of the gate insulating layer. A bottom surface of the shallow trench isolation structure is gradually decreasing in depth from the second sidewall to the first sidewall. A source/drain region is formed in the substrate at a side of the gate insulating layer and surrounding the shallow trench isolation structure.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: August 24, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Shin-Hung Li
  • Patent number: 11100959
    Abstract: A variable resistance memory device includes memory cell stacks arranged in a first direction, the memory cell stacks including a first memory cell stack and a second memory cell stack. Each of the memory cell stacks includes a plurality of word lines, each word line of the plurality of word lines extending in a second direction intersecting the first direction and arranged in a third direction intersecting the first and second directions, and a memory cell connected to each of the plurality of word lines. Each of the memory cells includes a switching element and a variable resistance element. Each of the plurality of word lines of the first memory cell stack have a first thickness, in the first direction, of first word lines of the first memory cell stack is less than a second thickness, in the first direction, of each of the plurality of word lines of the second memory cell stack.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: August 24, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-Rie Sim, Taehui Na
  • Patent number: 11094586
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: August 17, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hoon Choi, Jaeung Koo, Kwansung Kim, Bo Yun Kim, Wandon Kim, Boun Yoon, Jeonghyuk Yim, Yeryung Jeon
  • Patent number: 11079640
    Abstract: A method for repairing a white defect of a LCD panel includes providing a substrate, the substrate defining pixel areas which themselves comprise a base, a first metal layer, a first insulating layer, a semi-conductor layer, an ohmic contact layer, a source electrode, a drain electrode, and a second insulating layer; forming a through hole by laser in the second insulating layer, the through hole extending through the second insulating layer and separating the drain electrode into two spaced parts; forming a third insulating layer to cover the first conductive layers, the second insulating layer and the though hole and forming a second conductive layer by laser on the third insulating layer to couple the first conductive layer to the second conductive layer.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 3, 2021
    Assignee: Century Technology (Shenzhen) Corporation Limited
    Inventors: Yuan Xiong, Chih-Chung Liu, Ming-Tsung Wang, Meng-Chieh Tai
  • Patent number: 11081640
    Abstract: Embodiments of the invention are directed to a method of forming a bottom electrode of a magnetic tunnel junction (MTJ) storage element. A non-limiting example of the method includes forming the bottom electrode of the MTJ storage element such that the bottom electrode is communicatively coupled to an interconnect structure through an in-situ interface, wherein the in-situ interface includes an interface between a bottom surface of the bottom electrode and a top surface of the interconnect structure. A top surface of the bottom electrode is configured to couple to a bottom end of a MTJ stack, and the bottom electrode includes a semiconductor and metal alloy.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: August 3, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 11081494
    Abstract: A semiconductor memory according to an embodiment includes a first conductor, a first insulator and memory pillars. The first conductor and the first insulator are alternately stacked along a first direction. The memory pillars penetrates through the stacked first conductor and first insulator. Each of the memory pillars include a semiconductor, a tunnel insulating film, a second insulator, and a block insulating film. The memory pillars include a first memory pillar. The stacked first insulator includes a first layer and a second layer that are adjacent to each other in the first direction. The first conductor between the first layer and the second layer includes a first conductive part, a second conductive part, and a first dissimilar conductive part.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 3, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Masanari Fujita
  • Patent number: 11069876
    Abstract: An organic electroluminescence display device has a plurality of pixels, each of the pixels including a first portion and a second portion. The first portion has an organic light emitting element and is configured to display images. The second portion is a transparent transmission area through which an external object is visible and includes a foreign substance collecting member. The foreign substance collecting member is made of a ferromagnetic substance and is configured to receive electric current from an external current source through a connecting line and an electric field application pad. When electric current is applied to the electric field application pad, a magnetic field is applied to the foreign substance collecting member, and foreign substance in the first portion is collected by the foreign substance collecting member in the second portion, preventing the foreign substance from being deposited in the first portion.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: July 20, 2021
    Assignee: LG Display Co., Ltd.
    Inventor: Sungsoo Gil
  • Patent number: 11069619
    Abstract: An interconnect structure and an electronic device including the interconnect structure are disclosed. The interconnect structure may include a metal interconnect having a bottom surface and two opposite side surfaces surrounded by a dielectric layer, a graphene layer on the metal interconnect, and a metal bonding layer providing interface adhesion between the metal interconnect and the graphene layer. The metal bonding layer includes a metal material.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seunggeol Nam, Hyeonjin Shin, Keunwook Shin, Changhyun Kim, Kyung-Eun Byun, Hyunjae Song, Eunkyu Lee, Changseok Lee, Alum Jung, Yeonchoo Cho
  • Patent number: 11069721
    Abstract: Disclosed are a display device for preventing loss of line patterns and a method of manufacturing the display device. The display device includes a substrate having an active area, a non-active area, and a pad portion formed at one side of the non-active area, printed circuit films disposed in the pad portion so as to be spaced a first distance apart from an edge of the substrate in a first direction and to be spaced apart from each other in a second direction that intersects the first direction, a first-layer line and a second-layer line disposed within the first distance between the printed circuit films and the edge of the substrate so as to be spaced apart from each other in the first direction, and island-shaped dummy patterns disposed in the same layer as the second-layer line in a region between two adjacent ones of the printed circuit films.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: July 20, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: Won-June Jung, Sang-Moo Park, Seok-Hyun Lee
  • Patent number: 11056594
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region adjacent to the well pick-up region. The semiconductor device structure also includes a first fin structure with a first width and a third fin structure with a third width formed adjacent to each other in the well pick-up region and a second fin structure with a second width and a fourth fin structure with a fourth width formed adjacent to each other in the active region. The first width is different than the second width, the third width is different than the fourth width, and the first width is substantially equal to or greater than the third width.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 6, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang