Patents Examined by Steven H. Loke
  • Patent number: 10388729
    Abstract: Devices and methods of fabricating integrated circuit devices for forming uniform nano sheet spacers self-aligned to the channel are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate, multiple layers disposed on the substrate, and at least one gate structure disposed on the multiple layers; depositing an oxide layer over the device; etching the oxide layer to form replacement sidewall spacers positioned on left and right sides of the at least one gate structure; etching the multiple layers to form at least one stack structure; and forming a plurality of recesses within the at least one stack structure. Also disclosed is an intermediate semiconductor, which includes, for instance: a substrate; and at least one stack structure disposed on the substrate, the at least one stack structure having an upper portion and a base portion, wherein a plurality of recesses are located within the base portion.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: John Zhang, Lawrence Clevenger, Kangguo Cheng, Balasubramanian Haran
  • Patent number: 10371997
    Abstract: The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: August 6, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD, BEIJING BOE DISPLAY TECHNOLOGY CO., LTD
    Inventors: Xiaowei Liu, Xi Chen, Zhenfei Cai, Yao Liu, Liangliang Li, Zongjie Guo
  • Patent number: 10366940
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10354975
    Abstract: An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: July 16, 2019
    Assignee: Raytheon Company
    Inventors: Edward R. Soares, John J. Drab
  • Patent number: 10340433
    Abstract: A light-emitting element disclosed in an embodiment comprises: a body having a cavity; first and second lead frames arranged in the cavity; a third lead frame arranged between the first and second lead frames in the cavity; a fourth lead frame arranged between the first and second lead frames and distanced from the third frame in the cavity; a first light-emitting chip arranged on the first lead frame; and a second light-emitting chip arranged on the second lead frame, wherein the body comprises: first and second sides arranged on opposing sides from each other; and third and fourth sides arranged on opposing sides from each other, the first lead frame comprises first and second lead parts protruding toward the first and second sides, the second lead frame comprises third and forth lead parts protruding toward the first and second sides, the third frame comprises a fifth lead part protruding toward the first side, and the fourth lead frame comprises a sixth lead part protruding toward the second side.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: July 2, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Tae Sung Lee, Sung Min Kong, Young Min Ryu, Jae Hwan Jung, Jong Beom Choi
  • Patent number: 10332780
    Abstract: A semiconductor device includes a substrate having a first active pattern and a second active pattern, the first active pattern including a first recess region dividing an upper portion thereof into a first portion and a second portion, the second active pattern including a second recess region dividing an upper portion thereof into a first portion and a second portion, a first insulating pattern covering an inner sidewall of the first recess region, and a second insulating pattern covering an inner sidewall of the second recess region. The first insulating pattern and the second insulating pattern include the same insulating material, and a volume fraction of the first insulating pattern with respect to a volume of the first recess region is smaller than a volume fraction of the second insulating pattern with respect to a volume of the second recess region.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunki Min, Songe Kim, Koungmin Ryu, Je-Min Yoo
  • Patent number: 10332894
    Abstract: A semiconductor device and method for fabricating the same are provided. The semiconductor device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region of the substrate to separate the cell region from the core region, a high-k dielectric layer on at least a part of the boundary element isolation layer and the core region of the substrate, a first work function metal pattern comprising a first extension overlapping the boundary element isolation layer on the high-k dielectric layer, and a second work function metal pattern comprising a second extension overlapping the boundary element isolation layer on the first work function metal pattern, wherein a first length of the first extension is different from a second length of the second extension.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ki Wook Jung, Dong Oh Kim, Seok Han Park, Chan Sic Yoon, Ki Seok Lee, Ho In Lee, Ju Yeon Jang, Je Min Park, Jin Woo Hong
  • Patent number: 10325876
    Abstract: The present disclosure provides embodiments of package devices and methods for making package devices for a semiconductor die. One embodiment includes a die mounting structure having a finished bond pad that includes a copper bond pad and a cobalt-containing layer over a top surface of the copper bond pad, and a wire bond structure that is bonded to a top surface of the cobalt-containing layer of the finished bond pad, where cobalt-containing material of the cobalt-containing layer is located between a bottom surface of the wire bond structure and the top surface of the copper bond pad such that the cobalt-containing material is present under a center portion of the wire bond structure.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: June 18, 2019
    Assignee: NXP USA, Inc.
    Inventors: Varughese Mathew, Burton J. Carpenter, Leo M. Higgins, III, Chu-Chung Lee, Tu-Anh N. Tran
  • Patent number: 10304833
    Abstract: A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: May 28, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Puneet Harischandra Suvarna, Bipul C. Paul, Ruilong Xie, Bartlomiej Jan Pawlak, Lars W. Liebmann, Daniel Chanemougame, Nicholas V. LiCausi, Andreas Knorr
  • Patent number: 10283554
    Abstract: A semiconductor device may include a first sensor configured to sense light having a wavelength within a first wavelength range from incident light and generates a first electrical signal based on the sensed light and a second sensor configured to sense light having a wavelength within a second, different wavelength range from the incident light and generates a second electrical signal based on the sensed light. The first and second sensors may be electrically connected to each other via an intermediate connector, and the first sensor and the second sensor may share a pixel circuit that is electrically connected thereto via the intermediate connector. The first and second wavelength ranges may include infra-red and visible wavelength ranges, respectively. The first and second wavelength ranges may include different visible wavelength ranges.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: May 7, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Gu Jin, Doo Won Kwon
  • Patent number: 10283686
    Abstract: An optoelectronic semiconductor component includes an optoelectronic semiconductor chip; and an electrical connection point that contacts the optoelectronic semiconductor chip, wherein the electrical connection point covers the optoelectronic semiconductor chip on the bottom thereof at least in some areas, the electrical connection point includes a contact layer facing toward the optoelectronic semiconductor chip, the electrical connection point includes at least one barrier layer arranged on a side of the contact layer facing away from the optoelectronic semiconductor chip, the electrical connection point includes a protective layer arranged on the side of the at least one barrier layer facing away from the contact layer, the layers of the electrical connection point are arranged one on top of another along a stack direction, and the stack direction runs perpendicular to a main extension plane of the optoelectronic semiconductor chip.
    Type: Grant
    Filed: January 11, 2016
    Date of Patent: May 7, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Korbinian Perzlmaier, Anna Kasprzak-Zablocka, Stefanie Rammelsberger, Julian Ikonomov
  • Patent number: 10269620
    Abstract: Contacts to peripheral devices extending through multiple tier structures of a three-dimensional memory device can be formed with minimal additional processing steps. First peripheral via cavities through a first tier structure can be formed concurrently with formation of first memory openings. Sacrificial via fill structures can be formed in the first peripheral via cavities concurrently with formation of sacrificial memory opening fill structures that are formed in the first memory openings. Second peripheral via cavities through a second tier structure can be formed concurrently with formation of word line contact via cavities that extend to top surfaces of electrically conductive layers in the first and second tier structures. After removal of the sacrificial via fill structures, the first and second peripheral via cavities can be filled with a conductive material to form peripheral contact via structures concurrently with formation of word line contact via structures.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: April 23, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Zhenyu Lu, Hiroyuki Ogawa, Daxin Mao, Kensuke Yamaguchi, Sung Tae Lee, Yao-sheng Lee, Johann Alsmeier
  • Patent number: 10269802
    Abstract: A semiconductor device includes first and second Fin FETs and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction. When viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Han Lin
  • Patent number: 10263079
    Abstract: Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include forming a modulation doped heterostructure, comprising forming an active portion having a first bandgap and forming a delta doped portion having a second bandgap.
    Type: Grant
    Filed: December 17, 2016
    Date of Patent: April 16, 2019
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Mantu Hudait, Marko Radosavljevic, Willy Rachmady, Gilbert Dewey, Jack Kavalieros
  • Patent number: 10246320
    Abstract: Sensor packages and methods of assembling a sensor in a sensor package are provided. A preferred embodiment comprises: a base including a sensor coupled to the base wherein the base has at least one electrical connection location and a first mechanical mating interface in the shape of an arc; an electronics package with at least one electrical connection location; and a ring coupled between the base and the electronics package wherein the ring electrically connects the at least one electrical connection location on the base and the at least one electrical connection location on the electronics package and wherein the base has a second mechanical mating interface in the shape of an arc that is reciprocal to the first mating interface.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: April 2, 2019
    Assignee: DUNAN SENSING, LLC
    Inventors: Danny (Duy) Do, Tom Nguyen, Kevin Cuong Nguyen, Claudio Martinez
  • Patent number: 10242933
    Abstract: Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a gate on a substrate and over a channel region of a semiconductor fin. A contact is formed on a doped region of the substrate such that a space between the contact and the gate defines a trench. A first dielectric layer is formed over the gate and the contact such that the first dielectric layer partially fills the trench. A second dielectric layer is formed over the first dielectric layer such that an air spacer forms in the trench between the gate and the contact.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Griselda Bonilla, Elbert Huang, Son Nguyen, Takeshi Nogami, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 10224205
    Abstract: This present invention discloses a method for preparing graphene, a thin-film transistor, an array substrate, and a display panel. Above all, an amorphous carbon thin film and a catalyst metal thin film are formed on a base substrate in this order. Then, the catalyst metal thin film and the amorphous carbon thin film are allowed to form a eutectic at a high temperature caused by an excimer laser in a manner of excimer laser irradiation. When the irradiation is finished, the surface temperature of the catalyst metal thin film is drastically decreased, allowing most of carbon atoms of the amorphous carbon thin film to be locked in the catalyst metal thin film and only a small amount of carbon atoms to be precipitated on the lower surface of the catalyst metal thin film, so that a graphene thin film is formed.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: March 5, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Tuo Sun
  • Patent number: 10211392
    Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Ruchil Kumar Jain, Yongshun Sun, Shyue Seng Tan
  • Patent number: 10199480
    Abstract: A semiconductor structure includes a semiconductor substrate, a bottom source/drain layer for a first vertical transistor over the semiconductor substrate, a vertical channel over the source/drain layer, and a metal gate wrapped around the vertical channel, the vertical channel having a fixed height relative to the metal gate at an interface therebetween. The semiconductor structure further includes a top source/drain layer over the vertical channel, and a self-aligned contact to each of the top and bottom source/drain layer and the gate. The semiconductor structure can be realized by providing a semiconductor substrate with a bottom source/drain layer thereover, forming a vertical channel over the bottom source/drain layer, forming a dummy gate wrapped around the vertical channel, and forming a bottom spacer layer and a top spacer layer around a top portion and a bottom portion, respectively, of the vertical channel, a remaining center portion of the vertical channel defining a fixed vertical channel height.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Tenko Yamashita, Kangguo Cheng, Chun-Chen Yeh
  • Patent number: 10177279
    Abstract: Provided are a horizontal light emitting diode (LED) device and a method for fabricating the same. The horizontal LED device includes a sapphire substrate; an n-type GaN layer disposed on the sapphire substrate; an activation layer disposed on the n-type GaN layer; a p-type GaN layer disposed on the activation layer; a current spreading layer disposed on the p-type GaN layer; a p-electrode disposed on the current spreading layer; a plurality of holes exposing the n-type GaN layer through the current spreading layer, the p-type GaN layer, and activation layer; and an n-electrode disposed on the exposed n-type GaN layer and being in ohmic contact with the exposed n-type GaN layer at a plurality of positions on bottom surfaces of the plurality of holes.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: January 8, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Tae Yeon Seong, Ki Seok Kim, Junyong Jin