Patents Examined by Steven H. Loke
  • Patent number: 10784444
    Abstract: A light detection element including: a carbon nanotube structure; a first electrode and a second electrode, electrically connected to the carbon nanotube structure; wherein the carbon nanotube structure includes at least one carbon nanotube, the carbon nanotube includes two metallic carbon nanotube segments and one semiconducting carbon nanotube segment between the two metallic carbon nanotube segments, one of the two metallic carbon nanotube segments is electrically connected to the first electrode, the other one of the two metallic carbon nanotube segments is electrically connected to the second electrode.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: September 22, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Jiang-Tao Wang, Peng Liu, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10763381
    Abstract: Disclosed is an opto-electronic device including a semiconducting substrate, a layered interface including at least one layer, the layered interface having a first surface in contact with a surface of the semiconducting substrate and the layered interface being adapted for passivating the surface of the semiconducting substrate, the layered interface having a second surface and the layered interface being adapted for electrically insulating the first surface from the second surface, and a textured surface structure including a plurality of nanowires and a transparent dielectric coating, the textured surface structure being in contact with the second surface of the layered interface, the plurality of nanowires protruding from the second surface and the plurality of nanowires being embedded between the second surface and the transparent dielectric coating.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 1, 2020
    Assignees: TOTAL S.A., ECOLE POLYTECHNIQUE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Pere Roca I Cabarrocas, Wanghua Chen, Martin Foldyna, Gilles Poulain
  • Patent number: 10763427
    Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 1, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Ruchil Kumar Jain, Yongshun Sun, Shyue Seng Tan
  • Patent number: 10763324
    Abstract: A method is provided for forming an integrated thin film resistor (TFR) in a semiconductor integrated circuit device. A first dielectric layer is deposited on an integrated circuit (IC) structure including conductive contacts, a resistive film (e.g., comprising SiCCr, SiCr, CrSiN, TaN, Ta2Si, or TiN) is deposited over the first dielectric layer, the resistive film is etched to define the dimensions of the resistive film, and a second dielectric layer is deposited over the resistive film, such that the resistive film is sandwiched between the first and second dielectric layers. An interconnect trench layer may be deposited over the second dielectric layer and etched, e.g., using a single mask, to define openings that expose surfaces of the IC structure contacts and the resistive film. The openings may be filled with a conductive interconnect material, e.g., copper, to contact the exposed surfaces of the conductive contacts and the resistive film.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 1, 2020
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventor: Paul Fest
  • Patent number: 10763820
    Abstract: A method of manufacturing an electronic device formed in a cavity may include, on a first substrate having a bottom surface and a top surface, forming a first side wall of a certain height along a periphery on the bottom surface to surround an electronic circuit disposed on the bottom surface; forming a via communicating between the bottom surface and the top surface, forming of the via including stacking a first stop layer and a second stop layer sequentially on a portion of the bottom surface of the first substrate corresponding to the via and etching the first substrate to form a through-hole corresponding to the via, a rate of etching the first substrate being greater than that of the first stop layer and a rate of etching the first stop layer being greater than that of the second stop layer; forming a second side wall of a certain height along a periphery on a top surface of the second substrate; and aligning and bonding the first side wall and the second side wall.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: September 1, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventor: Atsushi Takano
  • Patent number: 10763292
    Abstract: A method includes bonding a first semiconductor chip on a second semiconductor chip, applying an etching process to the first semiconductor chip and the second semiconductor chip until a metal surface of the second semiconductor chip is exposed, wherein as a result of applying the etching process, an opening is formed in the first semiconductor chip and the second semiconductor chip and plating a conductive material in the opening to from a conductive plug.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jeng-Shyan Lin, Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung, Shih-Pei Chou, Min-Feng Kao, Szu-Ying Chen
  • Patent number: 10741661
    Abstract: The present disclosure relates to a conductive layer, a thin film transistor and manufacturing methods therefor, an array substrate and a display device, in the field of displays. The conductive layer comprises: a metal layer and an organophosphorus-metal complex covering the metal layer. In the embodiments of the present disclosure, the organophosphorus-metal complex is manufactured on the surface of the metal layer to form the conductive layer. The conductive layer is adopted as an electrode material. In one aspect, the organophosphorus-metal complex has conductivity and can prevent the surface of metal from making contact with oxygen, thereby avoiding metal oxidation under the premise of not affecting the performances of the electrode when serving as a material of the electrode in a TFT. In the other aspect, the organophosphorus-metal complex can increase a binding force between the metal and photoresist and avoids stripping of the photoresist.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: August 11, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Haixu Li
  • Patent number: 10741686
    Abstract: A method for manufacturing a semiconductor device according to an embodiment includes implanting impurity ions into a SiC layer in a direction of <10-11>±1 degrees, <10-1-1>±1 degrees, <10-12>±1 degrees, or <10-1-2>±1 degrees.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: August 11, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kono, Tomohiro Nitta
  • Patent number: 10734575
    Abstract: A method of forming a resistive random access memory device which contains uniform layer composition is provided. The method enables the in-situ deposition of a bottom electrode layer (i.e., a metal layer), a resistive switching element (i.e., at least one metal oxide layer), and a top electrode layer (i.e., a metal nitride layer and/or a metal layer) with compositional control. Resistive random access memory devices which contain uniform layer composition enabled by the in-situ deposition of the bottom electrode layer, the resistive switching element, and the top electrode layer provide significant benefits for advanced memory technologies.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Oscar van der Straten, Adra Carr, Praneet Adusumilli
  • Patent number: 10734283
    Abstract: A semiconductor device includes a first gate structure disposed on a substrate and extending in a first direction. The first gate structure includes a first gate electrode, a first cap insulating layer disposed over the first gate electrode, first sidewall spacers disposed on opposing side faces of the first gate electrode and the first cap insulating layer and second sidewall spacers disposed over the first sidewall spacers. The semiconductor device further includes a first protective layer formed over the first cap insulating layer, the first sidewall spacers and the second sidewall spacers. The first protective layer has a ?-shape having a head portion and two leg portions in a cross section along a second direction perpendicular to the first direction.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hui-Chi Chen, Hsiang-Ku Shen, Jeng-Ya David Yeh
  • Patent number: 10734514
    Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: August 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Romain Esteve, Dethard Peters, Roland Rupp, Ralf Siemieniec
  • Patent number: 10724065
    Abstract: The disclosure generally relates to a deoxyribonucleic acid (DNA) sequencing circuit having a controllable pore size and a lower membrane capacitance and noise floor relative to biological nanopore devices. For example, design principles used to fabricate a fin-shaped field effect transistor (FinFET) may be applied to form, on a first wafer, a nanopore that has a desired pore size in a silicon-based membrane. Electrodes and an interconnect embedded with an amplifier and analog-to-digital converter (ADC) may be formed on a separate second wafer, wherein the first wafer and the second wafer may then be bonded and further processed to form a sensing device that includes appropriate wells and pores to be used in a DNA sequencing circuit.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Yong Ju Lee, Joung Won Park
  • Patent number: 10727343
    Abstract: A semiconductor device structure is provided. The structure includes a semiconductor substrate having a well pick-up region and an active region. Each of the well pick-up region and the active region includes a first well region and a second well region that have different conductivity types. There is a well boundary between the first well region and the second well region. A first fin structure is in the first well region of the well pick-up region and second fin structures are in the first well region of the active region. The minimum distance between the well boundary and the first fin structure is greater than the minimum distance between the well boundary and one of the second fin structures that is closest to the well boundary.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Kuan Lin, Chang-Ta Yang, Ping-Wei Wang
  • Patent number: 10720455
    Abstract: A semiconductor crystal substrate includes a crystal substrate that is formed of a material including one of GaSb and InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb. The first buffer layer has a p-type conductivity, and the second buffer layer has an n-type conductivity.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: July 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Shigekazu Okumura, Shuichi Tomabechi, Ryo Suzuki
  • Patent number: 10714381
    Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes forming a first composite structure, including a plurality of first composite layers, on a substrate, and forming a second composite structure, including a plurality of second composite layers on a surface portion of the first composite structure. The method also includes forming a first mask layer covering a sidewall of the second composite structure and a surface portion of the first composite structure and exposing at least another surface portion of the first composite structure. In addition, the method includes forming a second mask layer, on a surface portion of the second composite structure and spaced apart from the first mask layer by a first annular opening. Further, the method includes etching a top first layer of the first composite layers and a top first layer of the second composite layers.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: July 14, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Rong Yao Chang, Yi Ying Zhang, Hai Yang Zhang
  • Patent number: 10707229
    Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: July 7, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Hyun Cho, Kwang Ho Lee, Ji Hwan Yu, Jong Soo Kim
  • Patent number: 10707439
    Abstract: The present disclosure provides a packaging adhesive, a packaging method, a display panel, and a display device. The packaging adhesive includes a frit, an organic solvent, and a material with a thermal expansion coefficient larger than that of the frit. Using the packaging adhesive provided by the present disclosure, the thermal expansion coefficient of the packaging adhesive from which the organic solvent is removed may be enhanced by doping the material with a thermal expansion coefficient larger than that of the frit into existing glass cement, so that in a packaging process using laser radiation, an expansion volume of the packaging adhesive when heated is increased. In this way, a gap between the packaging adhesive and an array substrate is effectively reduced, and a packaging effect is improved.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: July 7, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Chuan Yin, Chia Hao Chang, Xianjiang Xiong
  • Patent number: 10707261
    Abstract: A semiconductor device may include a first sensor configured to sense light having a wavelength within a first wavelength range from incident light and generates a first electrical signal based on the sensed light and a second sensor configured to sense light having a wavelength within a second, different wavelength range from the incident light and generates a second electrical signal based on the sensed light. The first and second sensors may be electrically connected to each other via an intermediate connector, and the first sensor and the second sensor may share a pixel circuit that is electrically connected thereto via the intermediate connector. The first and second wavelength ranges may include infra-red and visible wavelength ranges, respectively. The first and second wavelength ranges may include different visible wavelength ranges.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 7, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Gu Jin, Doo Won Kwon
  • Patent number: 10699992
    Abstract: An electronic assembly that includes a substrate having an aperture which extends through the substrate. The electronic assembly further includes a gull wing electronic package that includes leads which are solder mounted to the substrate such that the gull wing electronic package is within the aperture in the substrate, wherein the aperture is concentric with an exterior of the gull wing electronic package.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Juan Landeros, Jason M. Seitz, Mingjing Huang
  • Patent number: 10700266
    Abstract: An MTJ structure having vertical magnetic anisotropy is provided. The MTJ structure having vertical magnetic anisotropy can comprise: a substrate; an artificial antiferromagnetic layer located on the substrate; a buffer layer located on the artificial antiferromagnetic layer, and including W or an alloy containing W; a first ferromagnetic layer located on the buffer layer, and having vertical magnetic anisotropy; a tunneling barrier layer located on the first ferromagnetic layer; and a second ferromagnetic layer located on the tunneling barrier layer, and having vertical magnetic anisotropy. Accordingly, in the application of bonding the artificial antiferromagnetic layer with a CoFeB/MgO/CoFeB structure, the MTJ structure having improved thermal stability at high temperature can be provided by using the buffer layer therebetween.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: June 30, 2020
    Assignee: Industry-University Cooperation Foundation Hanyang University
    Inventors: Jin Pyo Hong, Ja Bin Lee