Patents Examined by Steven H. Rao
  • Patent number: 7724315
    Abstract: A liquid crystal display module, a liquid crystal display device, and a method for assembling the liquid crystal display device, which are capable of minimizing the overall size of the liquid crystal display device by improving an engaging structure between the liquid crystal display module and a case, are disclosed. Engaging holes are formed in an unused region of a top chassis, a mold frame and an end portion of a back cover. One side of a shaft screw is engaged with a catching member integrally formed with the inner side upper surface of a case. The other side of the shaft screw penetrates through the engaging holes of the top chassis, the mold frame, and the back cover and is engaged with a nut screw on a rear surface of the back cover. Accordingly, a separate space for installing a fixing member for fixing the mold frame and the back cover to the case is not needed, and the case, the mold frame, and the back cover is not engaged by using a separate screw.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: May 25, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Han Ryu, Hee-June Kwak
  • Patent number: 7723166
    Abstract: The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: May 25, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7718484
    Abstract: In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silicon surface to a first inert gas plasma. Thereafter a silicon compound layer is formed on the surface of the silicon gas by generating plasma while using a mixed gas of a second inert gas and one or more gaseous molecules, such that there is formed a silicon compound layer containing at least a pat of the elements constituting the gaseous molecules, on the surface of the silicon gas.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 18, 2010
    Assignee: Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Masaki Hirayama, Yasuyuki Shirai
  • Patent number: 7718994
    Abstract: Array substrates for use in TFT-LCDs and fabrication methods thereof. A transparent conductive layer, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer and a sacrificial layer are sequentially formed on a substrate. With a first photomask, a photoresist layer with various thicknesses is formed on part of the sacrificial layer. Using the photoresist layer as an etching mask, a gate line having a gate, a channel layer on the gate, a gate pad at the end portion of the gate line, a pixel electrode and a source pad are defined. An insulating spacer is formed on the sidewalls of the gate and gate line. With a second photomask, a source line, source and drain are formed. The source pad connects the end portion of the source line. An array substrate is thus obtained with only two photomasks.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: May 18, 2010
    Assignee: AU Optronics Corp.
    Inventor: Chun-Ju Huang
  • Patent number: 7714354
    Abstract: A method is provided for electroforming metal integrated circuit structures. The method comprises: forming an opening such as a via or line through an interlevel insulator, exposing a substrate surface; forming a base layer overlying the interlevel insulator and substrate surface; forming a strike layer overlying the base layer; forming a top layer overlying the strike layer; selectively etching to remove the top layer overlying the substrate surface, exposing a strike layer surface; and, electroforming a metal structure overlying the strike layer surface. The electroformed metal structure is deposited using an electroplating or electroless deposition process. Typically, the metal is Cu, Au, Ir, Ru, Rh, Pd, Os, Pt, or Ag. The base, strike, and top layers can be deposited using physical vapor deposition (PVD), evaporation, reactive sputtering, or metal organic chemical vapor deposition (MOCVD).
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: May 11, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: David R. Evans, John W. Hartzell
  • Patent number: 7709859
    Abstract: High electron mobility transistors are provided that include a non-uniform aluminum concentration AlGaN based cap layer having a high aluminum concentration adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. High electron mobility transistors are provided that include a cap layer having a doped region adjacent a surface of the cap layer that is remote from the barrier layer on which the cap layer is provided. Graphitic BN passivation structures for wide bandgap semiconductor devices are provided. SiC passivation structures for Group III-nitride semiconductor devices are provided. Oxygen anneals of passivation structures are also provided. Ohmic contacts without a recess are also provided.
    Type: Grant
    Filed: March 12, 2007
    Date of Patent: May 4, 2010
    Assignee: Cree, Inc.
    Inventors: Richard Peter Smith, Adam William Saxler, Scott T. Sheppard
  • Patent number: 7709302
    Abstract: A purpose of the invention is to provide a method for leveling a semiconductor layer without increasing the number and the complication of manufacturing processes as well as without deteriorating a crystal characteristic, and a method for leveling a surface of a semiconductor layer to stabilize an interface between the surface of the semiconductor layer and a gate insulating film, in order to achieve a TFT having a good characteristic. In an atmosphere of one kind or a plural kinds of gas selected from hydrogen or inert gas (nitrogen, argon, helium, neon, krypton and xenon), radiation with a laser beam in the first, second and third conditions is carried out in order, wherein the first condition laser beam is radiated for crystallizing a semiconductor film or improving a crystal characteristic; the second condition laser beam is radiated for eliminating an oxide film; and the third condition laser beam is radiated for leveling a surface of the crystallized semiconductor film.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: May 4, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Setsuo Nakajima
  • Patent number: 7709349
    Abstract: In one aspect, there is provided a method of manufacturing a semiconductor device that comprises placing a blocking layer, a CMP stop layer and a bulk oxide layer over an oxide cap layer that is located over gate structures and source/drains located adjacent thereto. The bulk oxide layer and the CMP stop layer are removed with a CMP process to expose the top of gate electrodes and are removed from over the source/drain areas with a wet etch. The CMP stop layer has a CMP removal rate that is less than a CMP removal rate of the bulk oxide layer and has a wet etch removal rate that is greater than a wet etch removal rate of the blocking layer.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: May 4, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Mark R. Visokay
  • Patent number: 7705691
    Abstract: A substrate for power decoupling and a method of forming a substrate for power decoupling. The substrate comprises one or more decoupling capacitors; and one or more interconnections to the decoupling capacitors. At least one of the interconnections comprises a lossy material.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: April 27, 2010
    Assignee: Agency for Science, Technology & Research
    Inventors: Chee Wai Albert Lu, Boon Keng Lok, Chee Khuen Stephen Wong, Kai Meng Chua, Lai Lai Wai, Sunnappan Vasudivan
  • Patent number: 7705386
    Abstract: A memory cell has an access transistor and a capacitor with an electrode disposed within a deep trench. STI oxide covers at least a portion of the electrode, and a liner covers a remaining portion of the electrode. The liner may be a layer of nitride over a layer of oxide. Some of the STI may cover a portion of the liner. In a memory array a pass wordline may be isolated from the electrode by the STI oxide and the liner.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: April 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Johnathan E. Faltermeier, Herbert L. Ho, Paul C. Parries
  • Patent number: 7700969
    Abstract: A semiconductor device exhibiting interband tunneling with a first layer with a first conduction band edge with an energy above a first valence band edge, with the difference a first band-gap. A second layer with second conduction band edge with an energy above a second valence band edge, with the difference a second band-gap, and the second layer formed permitting electron carrier tunneling transport. The second layer is between the first and a third layer, with the difference between the third valence band edge and the third conduction band edge a third band-gap. A Fermi level is nearer the first conduction band edge than the first valence band edge. The second valence band edge is beneath the first conduction band edge. The second conduction band edge is above the third valence band edge. The Fermi level is nearer the third valence band edge than to the third conduction band edge.
    Type: Grant
    Filed: January 30, 2007
    Date of Patent: April 20, 2010
    Assignee: HRL Laboratories, LLC
    Inventors: Joel N. Schulman, David H. Chow, Chanh Nguyen
  • Patent number: 7700980
    Abstract: Each of a pair of like-polarity IGFETs (40 or 42 and 240 or 242) has a channel zone (64 or 84) situated in body material (50). Short-channel effects are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 ?m deep into the body material but not more than 0.4 ?m deep into the body material. A pocket portion (100/102 or 104) extends along both source drain zones of one of the IGFETs. A pocket portion (244 or 246) extends largely along only one of the source/drain zones of the other IGFET so that it is an asymmetrical device.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: April 20, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala
  • Patent number: 7701066
    Abstract: A semiconductor wafer, a panel, and an electronic component, and also methods for producing them is disclosed. In this context, the electronic component has a stack of two semiconductor chips. The top stacked semiconductor chip is thin-ground and is arranged using flip-chip technology on a central region of the bottom semiconductor chip. An edge region of the bottom semiconductor chip contains vias through a leveling layer to a rewiring plane, which for its part carries external contacts.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: April 20, 2010
    Assignee: Infineon Technologies AG
    Inventor: Bernd Goller
  • Patent number: 7696537
    Abstract: A device, and method for manufacturing the same, including a PFET having an embedded SiGe layer where a shallow portion of the SiGe layer is closer to the PFET channel and a deep portion of the SiGe layer is further from the PFET channel. Thus, the SiGe layer has a boundary on the side facing toward the channel that is tapered. Such a configuration may allow the PFET channel to be compressively stressed by a large amount without necessarily substantially degrading extension junction characteristics. The tapered SiGe boundary may be configured as a plurality of discrete steps. For example, two, three, or more discrete steps may be formed.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: April 13, 2010
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Yusuke Kohyama
  • Patent number: 7696558
    Abstract: A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transist
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: April 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroomi Nakajima, Kazumi Inoh
  • Patent number: 7696586
    Abstract: A structure. The structure may include a layer of cobalt disilicide that is substantially free of cobalt monosilicide and there is substantially no stringer of an oxide of titanium on the layer of cobalt disilicide. The structure may include a substrate that includes: an insulated-gate field effect transistor (FET) that includes a source, a drain, and a gate; a first layer of cobalt disilicide on the source, said first layer having substantially no cobalt monosilicide, and said first layer having substantially no stringer of an oxide of titanium thereon; a second layer of cobalt disilicide on the drain, said second layer having substantially no cobalt monosilicide having substantially no stringer of an oxide of titanium thereon; and a third layer of cobalt disilicide on the gate, said third layer having substantially no cobalt monosilicide and having substantially no stringer of an oxide of titanium thereon.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: April 13, 2010
    Assignee: International Business Machines Corporation
    Inventors: David Paul Agnello, Mary Conroy Bushey, Donna K. Johnson, Jerome Brett Lasky, Peter James Lindgren, Kirk David Peterson
  • Patent number: 7696599
    Abstract: A trench MOSFET with drain (8), drift region (10) body (12) and source (14). In order to improve the figure of merit for use of the MOSFET as control and sync FETs, the trench (20) is partially filled with dielectric (24) adjacent to the drift region (10) and a graded doping profile is used in the drift region (10).
    Type: Grant
    Filed: November 26, 2004
    Date of Patent: April 13, 2010
    Assignee: NXP B.V.
    Inventors: Raymond J. E. Hueting, Erwin A. Hijzen
  • Patent number: 7687402
    Abstract: The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: March 30, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Arup Bhattacharyya
  • Patent number: 7687869
    Abstract: A semiconductor device according to the present invention comprises a semiconductor substrate, a gate insulating film which is composed of a material whose main component is a tetravalent metal oxide, a mixture of a tetravalent metal oxide and SiO2, or a mixture of a tetravalent metal oxide and SiON and which containing B when it is in an nMOS structure on the semiconductor substrate or containing at least one of P and As when it is in a pMOS structure on the semiconductor substrate, and a gate electrode made of a metal having a work function of 4 eV to 5.5 eV.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: March 30, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Kaneko, Seiji Inumiya, Katsuyuki Sekine, Kazuhiro Eguchi, Motoyuki Sato
  • Patent number: 7679663
    Abstract: A pixel section Pm,n includes a photodiode PD, a first capacitance section C1, a second capacitance section C2, and transistors T1-T6. The transistor T1 transfers the electric charge generated by the photodiode PD to the first capacitance section C1. The transistor T2 transfers the electric charge generated by the photodiode PD to the second capacitance section C2. The amplification transistor T3 outputs a voltage value corresponding to the amount of electric charge accumulated in the first capacitance section C1. The transistor T4 selectively outputs to the wiring L1,n the voltage value outputted from the amplification transistor T3. The transistors T3 and T4 constitute a source follower circuit. The transistors T5 and T6 selectively output to the wiring L2,n the electric charge accumulated in each of the first capacitance section C1 and the second capacitance section C2.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: March 16, 2010
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Yukinobu Sugiyama, Seiichiro Mizuno