Patents Examined by Steven Ho Vin Loke
  • Patent number: 5426327
    Abstract: A MOS-type semiconductor device having an LDD structure. The device includes a silicon substrate of a first conductivity type. An insulating film is formed on a main surface of the silicon substrate. A gate electrode made of polycrystalline silicon containing impurities at a first concentration is formed on the insulating film. Sidewall spacers made of polycrystalline silicon containing impurities at a second concentration different from the first concentration are formed at both sides of the gate electrode. Impurity diffusion layers are formed in the main surface of the semiconductor substrate at respective regions thereof where source and drain of the MOS-type semiconductor device are to be formed. Each of the impurity diffusion layers includes a low concentration diffusion layer disposed at a first portion of one of the regions and a high concentration diffusion layer disposed at a second portion other than the first portion of the one region.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: June 20, 1995
    Assignee: Nippon Steel Corporation
    Inventor: Ichiro Murai