Abstract: This disclosure describes auto-zero amplifier circuit that include an additional capacitor (or other capacitive component) that can be switchably coupler to a reference voltage. The auto-zero amplifier circuit can generate an auto-zero compensation signal using a difference between the reference voltage stored on the additional capacitor and a voltage stored on another auto-zero capacitor.

Abstract: In a gain control device, a gain control voltage adjust circuit includes a time-constant circuit and outputs an adjusted gain control voltage depending on an adjustment signal and a control voltage generated by a differential amplifier upon input of the adjustment signal. An adjustment signal generation circuit outputs the adjustment signal during an adjustment signal output period. This period is a specified period before a first burst signal is output from a signal output unit and where a burst signal is not output from the signal output unit. The adjustment signal is to make the adjusted gain control voltage closer to a target voltage. The target voltage is a gain control voltage output from the gain control voltage adjust circuit and corresponding to a steady part of a second burst signal. The second burst signal is a burst signal output before the first burst signal.

Abstract: A differential amplifier circuit includes a first input transistor that receives a signal supplied from the first input terminal via a gate thereof, a second input transistor that receives a signal supplied from the second input terminal via a gate thereof, and an offset voltage adjustment circuit that is connected to at least one between the first input terminal and the gate of the first input transistor and between the second input terminal and the gate of the second input transistor.

Abstract: A variable gain amplifier circuit is disclosed. In one embodiment, an amplifier circuit includes first and second stages. Each stage includes one or more inverter pairs, with one inverter of each pair coupled to receive an inverting component of a differential signal and the other inverter of the pair coupled to receive a non-inverting component. The first stage receives a differential input signal and produces an intermediate differential signal. The second stage receives the intermediate differential signal and produces a differential output signal, the differential output signal being an amplified version of the differential input signal.

Abstract: A power efficient (PE) amplifier includes a cascode amplifier, a transistor amplifier, and a voltage supply. The transistor amplifier includes at least one differential pair of transistors and a plurality of transformers having a primary winding and a tapped secondary winding. The secondary winding is connected across emitters or sources of each transistor pair. The tap of each secondary has a current source. The primary windings of the plurality of transformers are connected in series. The transistor bases or gates are alternating current (AC) grounded. The collector or drain terminal pairs are connected in parallel. The voltage supply is low voltage and supplies a current to the cascode amplifier. The PE amplifier further includes a plurality of current sources which provide a total current to the transistor amplifier. The PE amplifier has, among other things, improved power gain, improved reverse isolation, improved power dissipation, and improved peak differential swing.

Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

Abstract: A first transistor, a second transistor, a third transistor, and a fourth transistor, their source terminals being grounded, are provided. Further, a first feedback circuit connected between a gate terminal and a drain terminal in the first transistor, and having first impedance, a second feedback circuit connected between a gate terminal and a drain terminal in the second transistor, and having the first impedance, a current source for outputting a current, a first load circuit connected between the drain terminal of the first transistor and a first output terminal of the current source, and having second impedance, and a second load circuit connected between the drain terminal of the second transistor and a second output terminal of the current source, and having the second impedance are provided.

Abstract: A power supply circuit comprises a power conversion circuit, a voltage selection circuit, and a voltage regulator. The voltage regulator coupled to the voltage selection circuit and a digital-to-analog converter (DAC), and the voltage regulator is configured to provide supply power to the DAC; the power conversion circuit is coupled to a first power supply and a power amplifier (PA), and the power conversion circuit is configured to convert, based on output power of the PA, a voltage of the first power supply into an output voltage that supply power to the PA; and the voltage selection circuit is coupled to a second power supply, the power conversion circuit and the voltage regulator, and the voltage selection circuit is configured to select the second power supply or the power conversion circuit to supply power to the voltage regulator based on an output voltage of the power conversion circuit.

Abstract: A power amplifier module includes an amplifier that amplifies an input signal and outputs the amplified signal, a harmonic termination circuit that is disposed subsequent to the amplifier and that attenuates a harmonic component of the amplified signal, the harmonic termination circuit including at least one field effect transistor (FET), and a control circuit that controls a gate voltage of the at least one FET to adjust a capacitance value of a parasitic capacitance of the at least one FET. The control circuit adjusts the capacitance value of the parasitic capacitance of the at least one FET, and thereby a resonance frequency of the harmonic termination circuit is adjusted.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an amplifier integrated circuit. The amplifier integrated circuit may provide two amplifiers, one amplifier set to a low gain bandwidth product to amplify at a higher speed and the other amplifier set to a high gain bandwidth product to amplify at a lower speed. The amplifier integrated circuit may further provide a switching circuit connected to the amplifiers, wherein the switching circuit is responsive to a control signal and operates to selectively activate the high speed amplifier and the low speed amplifier in sequence.

Abstract: An envelope tracking system is disclosed having an envelope tracking integrated circuit (ETIC) with a first tracker having a first supply output and a second tracker having a second supply output, wherein the ETIC has a first mode in which only one of the first and second trackers supplies voltage and a second mode in which the first and second trackers both supply voltage. A first notch filter is coupled to the first supply output and a second notch filter is coupled to the second supply output. A mode switch coupled between the first supply output and the second supply output is configured to couple the first notch filter and the second notch filter in parallel in the first mode and open the mode switch to decouple the first notch filter from the second notch filter in the second mode in response to first and second switch control signals, respectively.

Abstract: Disclosed herein are methods for amplifying a signals. The methods include receiving signals at a plurality of input nodes. The methods also include configuring a gain stage to be in a selected one of a plurality of gain settings, at least some of the gain settings resulting in different impedances presented to the signal. The methods also include adjusting the resistance presented to the signal by the gain stage for the selected gain setting, the adjusted resistance being configured to provide a targeted constant value of the impedance at the input across the plurality of gain settings. The methods also include amplifying at least a portion of the received signals. Adjusting the resistance compensates for changes to the input impedance to improve return loss and mismatch over gain modes.

Abstract: A circuit includes a first amplifier having first and second inputs and first and second output, first and second input capacitors, a first feedback capacitor selectively coupled between the first input and the first output, and a second feedback capacitor selectively coupled between the second input and the second output. During a second phase of operation, the first and second feedback capacitors are decoupled from the output and the first amplifier is configured to sample an input common mode voltage, an output common mode voltage, and an input offset voltage of the first amplifier on the first and second input capacitors. During a first phase of operation, the first feedback capacitor is coupled between the input and the output, the second feedback capacitor is coupled between the input and the output, and the first amplifier is configured to amplify a differential input signal provided across the first and second inputs.

Abstract: A power amplifier includes a first amplifier configured to output a signal based on a difference between an input signal and a feedback signal; a second amplifier that amplifies the power of the signal output from the first amplifier and outputs the amplified signal; a first feedback circuit that feeds the signal output from the second amplifier back to the first amplifier; a third amplifier that amplifies the power of the signal output from the second amplifier and outputs the amplified signal; and a second feedback circuit that feeds the signal output from the third amplifier back to the first amplifier, in which the feedback signal is a signal obtained by combining an output signal of the first feedback circuit with an output signal of the second feedback circuit.

Abstract: A chopper-stabilized current feedback amplifier includes an input buffer having a non-inverting input and an inverting input. A first group of chopper circuits modulate current at the non-inverting and inverting inputs. The current feedback amplifier further includes a plurality of current mirrors coupled to the input buffer. A second group of chopper circuits modulate current in the current mirrors. The current feedback amplifier also includes phase detector circuitry coupled to the current mirrors and configured to detect a transition current in the current mirrors. The current feedback amplifier also includes a switched capacitor filter having an input coupled to the current mirrors. The switched capacitor filter is turned OFF responsive to the detection of the transition current by the phase detector circuitry. The current feedback amplifier also includes an output stage having an input coupled to the switched capacitor filter and is configured to produce an output signal.

Abstract: This technology relates to a single-phase differential conversion circuit for improving the linearity of input/output characteristics, a signal processing method for use with the circuit, and a reception apparatus. The single-phase differential conversion circuit includes a first source-grounded amplifier and a second source-grounded amplifier. Each of the amplifiers includes a transconductance amplifier section including a transistor for converting an AC component of input potential to a current, a diode load section including a transistor in a diode connection configured as a first load, and a large-signal distortion compensation circuit configured as a second load connected in parallel with the first load. The transistors of the first source-grounded amplifier are each a P-type MOS transistor, and the transistors of the second source-grounded amplifier are each an N-type MOS transistor. This technology is applied advantageously to a reception apparatus for receiving TV signals, for example.

Abstract: Examples disclosed herein relate to a Doherty Power Amplifier (“DPA”) with integrated second harmonic injection. The DPA includes an amplifier circuit having a carrier amplifier and a peaking amplifier, and a combiner network coupled to the amplifier circuit, the combiner network having a plurality of transmission lines and a LC resonant circuit to inject a second harmonic from the carrier amplifier into the peaking amplifier.

Abstract: Embodiments of systems and method for automatically biasing power amplifiers using a controllable current source are disclosed. In an embodiment, a bias controller for a power amplifier includes a first reference device source/drain interface, a first controllable current source configured to generate a first reference current in response to a first current control signal and to provide the first reference current to the first reference device source/drain interface, a first reference device gate interface, a first current-to-voltage controller configured to generate a first stabilized voltage in response to the first reference current and to provide the first stabilized voltage to the first reference device gate interface, and a first power amplifier (PA) interface configured to output a first control voltage in response to the first stabilized voltage.

Abstract: In at least one embodiment, an interface electronic circuit for a capacitive acoustic transducer having a sensing capacitor is provided. The interface electronic circuit includes an amplifier, a voltage regulator, a common-mode control circuit, and a reference generator. The amplifier has an input coupled to an electrode of the sensing capacitor. The voltage regulator is configured to receive a regulator reference voltage, generate a regulated voltage based on the regulator reference voltage, and supply the regulated voltage to a supply input of the amplifier. The common-mode control circuit controls a common-mode voltage present on the input of the amplifier based on a common-mode reference voltage. The reference generator receives a supply voltage and generates the regulator reference voltage and the common-mode reference voltage with respective values that are variable as a function of the supply voltage.

Abstract: Systems and methods are provided for improved noise performance of audio amplifiers. In one example, a system includes a multistage amplifier comprising at least a first stage amplifier and a second stage amplifier. The system further includes a plurality of switches disposed within the multistage amplifier to configure the multistage amplifier. The system further includes a control signal configured to control the multistage amplifier to a normal amplification mode or a mute state, wherein the multistage amplifier is adapted to amplify an input signal in the normal amplification mode, the multistage amplifier is adapted to output a zero signal in the mute state, and internal amplification stages of the multistage amplifier are disabled in the mute state, and output stages of each of the at least first stage amplifier and the second stage amplifier are electrically shorted and/or shorted to a fixed bias voltage in the mute state.