Patents Examined by Su C. Kim
  • Patent number: 10658452
    Abstract: A display apparatus includes a substrate including a display area and a peripheral area disposed outside of the display area, a plurality of wiring lines disposed in the peripheral area, and an interlayer insulating layer covering the plurality of wiring lines. The interlayer insulating layer includes an upper surface having a first concave-convex surface corresponding to the plurality of wiring lines. The display apparatus further includes a first conductive layer disposed on the interlayer insulating layer and including a second upper surface having a second concave-convex surface corresponding to the first concave-convex surface, a planarization layer disposed on the first conductive layer and having a flat upper surface, a second conductive layer disposed on the planarization layer and having a flat upper surface, and a polarization plate disposed on the second conductive layer.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: May 19, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chulhyun Choi, Zail Lhee, Keunsoo Lee, Kyungchan Chae, Kwangmin Kim, Wonkyu Kwak, Kiwook Kim, Yangwan Kim, Hyunjoon Kim, Jisu Na, Joongsoo Moon
  • Patent number: 10658248
    Abstract: Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming a mask layer on a top surface of the gate structure; forming pocket regions in the base substrate at both sides of the gate structure; after forming the pocket regions, forming a first protective portion covering a top surface of the mask layer and protruding from sidewall surfaces of the gate structure; and after forming the first protective portion, forming doped source/drain regions in the base substrate and portions of the pocket regions at both sides of the gate structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 19, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Zhao Xu Shen
  • Patent number: 10644125
    Abstract: A method of forming a semiconductor structure includes, providing a semiconductor layer, forming an interfacial layer over the semiconductor layer, depositing a high-k dielectric layer over the interfacial layer, forming a dummy gate electrode over the high-k dielectric layer, patterning the dummy gate electrode layer, the high-k dielectric layer, and the interfacial layer, resulting in a dummy gate electrode having a width less than a width of the high-k dielectric layer, forming spacers along sidewalls of the patterned dummy gate electrode, the high-k dielectric layer, and the interfacial layer, forming source/drain features, and replacing the dummy gate electrode with a metal gate electrode to form a high-k metal gate structure.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jen-Hsiang Lu, Tsung-Han Tsai, Shih-Hsun Chang
  • Patent number: 10644173
    Abstract: An optical sensor includes a semiconductor substrate having a first conductive type. The optical sensor further includes a photodiode disposed on the semiconductor substrate and a metal layer. The photodiode includes a first semiconductor layer having the first conductive type and a second semiconductor layer, formed on the first semiconductor layer, including a plurality of cathodes having a second conductive type. The first semiconductor layer is configured to collect photocurrent upon reception of incident light. The cathodes are configured to be electrically connected to the first semiconductor layer and the second semiconductor layer is configured to, based on the collected photocurrent, to track the incident light. The metal layer further includes a pinhole configured to collimate the incident light, and the plurality of cathodes form a rotational symmetry of order n with respect to an axis of the pinhole.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: James Becker, Henry Litzmann Edwards
  • Patent number: 10629668
    Abstract: A display panel and a display device are provided. The display panel includes a display region, at least one notch, and a non-display region surrounding the display region. The display region includes an irregularly-shaped edge. The at least one notch is formed by recessing the irregularly-shaped edge toward an inside of the display region. The display panel also includes an array layer disposed on a side of a base substrate. The array layer includes at least one inorganic layer, the at least one inorganic layer including at least one protruded portion. In addition, the display panel includes a display function layer disposed on a side of the array layer away from the base substrate. Further, the display panel includes at least one blocking part formed in the non-display region. The at least one blocking part is disposed around the display region and around the display function layer.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: April 21, 2020
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Guofeng Zhang, Tianqing Hu
  • Patent number: 10629506
    Abstract: Disclosed is a preform for semiconductor encapsulation, mainly containing a metal or alloy, the metal or alloy further containing Sn or Sn alloy, and, Cu or Cu alloy, and still further containing at least 2% by weight of an intermetallic compound of Cu and Sn.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: April 21, 2020
    Assignee: Napra Co., Ltd.
    Inventors: Shigenobu Sekine, Chihiro Shimaya
  • Patent number: 10629521
    Abstract: An object of this invention is to obtain a molded module with which improvements are achieved in the packaging ability and heat dissipation performance of an inverter module itself, and in the mounting capacity of a peripheral mounting component such as a substrate, which must be taken into consideration in relation to the shape of the module. Provided is a molded module for use in power electronics, having an inbuilt semiconductor element used to supply and control a large amount of power, the molded module including at least one semiconductor switching element provided in the module and a lead frame that dissipates heat from the switching element and electrically connects an element packaged in the module to an external circuit, wherein at least one end of the module is molded in a curved shape or a polygonal shape.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: April 21, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takahiro Okanoue, Masaaki Tanigawa, Kensuke Takeuchi
  • Patent number: 10593542
    Abstract: According to an embodiment, a manufacturing method of a semiconductor device includes: carrying a substrate alternately stacked an electrode layer and an insulation layer into a chamber; increasing the temperature in the chamber to a predetermined temperature; and supplying hydrogen and material gas including metal simultaneously into the chamber, and supplying oxidizing gas the partial pressure ratio of which to the hydrogen is set so as to provide an atmosphere of reducing the electrode layer, by using an ALD method, and thereby forming, on a surface of the electrode layer and a surface of the insulation layer, a metal oxide layer obtained by oxidizing the metal.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Furuhashi, Masayuki Tanaka, Shinji Mori, Kenichiro Toratani
  • Patent number: 10586856
    Abstract: A semiconductor device is described. The semiconductor device includes a nanosheet stack including a sacrificial nanosheet oriented substantially parallelly to a substrate and a channel nanosheet disposed on the sacrificial nanosheet. The semiconductor device includes a gate formed in a direction orthogonal to the plane of the nanosheet stack, with a gate spacer positioned along a sidewall of the gate. The semiconductor device includes an inner spacer liner deposited around the nanosheet stack and the gate spacer. A first etching of the inner spacer liner is configured to produce an outer profile of the inner spacer liner, the outer profile having a substantially flat side section relative to an edge of the channel nanosheet. A second etching of the inner spacer liner is configured to remove substantially all material of the inner spacer liner from the edge of the channel nanosheet.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nicolas Loubet, Julien Frougier, Wenyu Xu, Zhenxing Bi
  • Patent number: 10566365
    Abstract: An image sensor includes a sensing layer, a first microlens, and a number of second microlenses. The first microlens is disposed on the sensing layer. The second microlenses are disposed on the sensing layer adjacent to the first microlens. The diameter of the first microlens is greater than the diameter of each of the second microlenses.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: February 18, 2020
    Assignee: VISERA TECHNOLOGIES COMPANY LIMITED
    Inventors: Li-Wei Chen, Chi-Han Lin, Zong-Ru Tu
  • Patent number: 10546746
    Abstract: A process of growing a barrier layer made of AlGaN on a GaN channel layer is disclosed. The process includes steps of, growing the GaN channel layer, growing the AlGaN barrier layer, and growing a cap layer made of GaN. The growth temperature of the AlGaN barrier layer monotonically lowers from the initial temperature, which may be equal to the growth temperature for the GaN channel layer, to the finish temperature that is lower than the initial temperature and may be substantially equal to the growth temperature of the GaN cap layer.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 28, 2020
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Hajime Matsuda
  • Patent number: 10544039
    Abstract: Methods for depositing a measured amount of a species in a sealed cavity. In one example, a method for depositing molecules in a sealed cavity includes depositing a selected number of microcapsules in a cavity. Each of the microcapsules contains a predetermined amount of a first fluid. The cavity is sealed after the microcapsules are deposited. After the cavity is sealed the microcapsules are ruptured to release molecules of the first fluid into the cavity.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 28, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Kurt Wachtler, Adam Joseph Fruehling, Juan Alejandro Herbsommer, Simon Joshua Jacobs
  • Patent number: 10515972
    Abstract: Some embodiments include apparatuses and methods having a source material, a dielectric material over the source material, a select gate material over the dielectric material, a memory cell stack over the select gate material, a conductive plug located in an opening of the dielectric material and contacting a portion of the source material, and a channel material extending through the memory cell stack and the select gate material and contacting the conductive plug.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: December 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Fatma Arzum Simsek-Ege, Krishna K. Parat, Luan C. Tran, Meng-Wei Kuo, Yushi Hu
  • Patent number: 10516062
    Abstract: In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide semiconductor film has an amorphous structure or a microcrystalline structure, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: December 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Patent number: 10504965
    Abstract: Solid-state imaging devices, electronic apparatuses, and methods of forming image sensors are provided. A solid-state imaging device or an electronic apparatus incorporating a solid-state imaging device can include a substrate and at least a first photoelectric conversion element formed in the substrate. In addition, a region with a low dielectric constant is formed. The region can include a locally thin region formed in the substrate. An insulating film is at the first side of the substrate. Where the region includes a locally thin region, the interlayer insulating film can extend into that locally thin region. A first electrode is at a side of the interlayer insulating film opposite the substrate. The device further includes a second electrode, and a photoelectric conversion layer at least partially between the first electrode and the second electrode.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: December 10, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Tetsuji Yamaguchi, Satoshi Keino
  • Patent number: 10490663
    Abstract: The present disclosure provides N-type fin field-effect transistors. An N-type fin field-effect transistor includes a semiconductor substrate; at least one fin having a first side surface and a second side surface formed over the semiconductor substrate; a gate structure crossing over the fin and formed over the semiconductor substrate; and a source region and a drain region respectively formed on top of the fin at two sides of the gate structure by an ion implantation process on one of the first side surface and the second side surface of the fin at two sides of the gate structure and a thermal annealing process to diffuse doping ions into the other of the first side surface and the second side surface of the fin.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 26, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 10475824
    Abstract: The present disclosure provides a display panel, its manufacturing method and a display device. The manufacturing method of the display panel comprises: forming, on a substrate, a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode; forming a hydrogen diffusion barrier layer that covers the entire substrate, wherein the hydrogen diffusion barrier layer is electrically conductive and is electrically connected to the drain electrode; and forming a photosensitive structure layer on the hydrogen diffusion barrier layer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: November 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Qingrong Ren, Woobong Lee, Fengchao Wang, Jianming Sun, Yingwei Liu, Wei Yang, Dongsheng Li
  • Patent number: 10468482
    Abstract: A method includes forming a crown structure over a substrate; forming fins in the crown structure; forming an intra-device isolation region between the fins and forming inter-device isolation regions on opposing sides of the crown structure; forming a gate structure over the fins; forming a dielectric layer that extends continuously over the inter-device isolation regions, the fins and the intra-device isolation region; performing an etching process to reduce a thickness of the dielectric layer, where after the etching process, upper surfaces of the inter-device isolation regions and upper surfaces of the fins are exposed while an upper surface of the intra-device isolation region is covered by a remaining portion of the dielectric layer; and forming an epitaxial structure over the exposed upper surfaces of the fins, where after the epitaxial structure is formed, there is a void between the epitaxial structure and the intra-device isolation region.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Li-Li Su, Tzu-Ching Lin
  • Patent number: 10468376
    Abstract: Disclosed is a semiconductor device that includes a semiconductor chip; bonding pads provided to the semiconductor chip; a plurality of lead terminals arranged around the semiconductor chip; a plurality of bonding wires that electrically connect the semiconductor chip with the plurality of lead terminals; and a resin encapsulant which encapsulates the semiconductor chip and the bonding wires, the semiconductor device further having an insulating material interposed at the interface between the bonding wires and the resin encapsulant, and the insulating material containing a nanometer-sized insulating particle and amorphous silica.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: November 5, 2019
    Assignee: Napra Co., Ltd.
    Inventor: Shigenobu Sekine
  • Patent number: 10461134
    Abstract: A technique of manufacturing a display device with high productivity is provided. In addition, a high-definition display device with high color purity is provided. By adjusting the optical path length between an electrode having a reflective property and a light-emitting layer by the central wavelength of a wavelength range of light passing through a color filter layer, the high-definition display device with high color purity is provided without performing selective deposition of light-emitting layers. In a light-emitting element, a plurality of light-emitting layers emitting light of different colors are stacked. The closer the light-emitting layer is positioned to the electrode having a reflective property, the shorter the wavelength of light emitted from the light-emitting layer is.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 29, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Seo, Toshiki Sasaki, Nobuharu Ohsawa, Takahiro Ushikubo, Shunpei Yamazaki