Patents Examined by Suberr L Chi
  • Patent number: 11367747
    Abstract: Monolithic pixel detectors, systems and methods for the detection and imaging of electromagnetic radiation with high spectral and spatial resolution comprise a Si wafer with a CMOS processed pixel readout bonded to an absorber wafer in wafer bonds comprising conducting bonds between doped, highly conducting charge collectors in the readout and highly conducting regions in the absorber wafer and poorly conducting bonds between regions of high resistivity.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 21, 2022
    Inventor: Hans Von Känel
  • Patent number: 11362233
    Abstract: An electrical readout optical sensor, includes a back metal electrode layer, a semiconductor layer, and a metal or metalloid layer; wherein the semiconductor layer is a main body portion and is divided into a first surface and a second surface; the first surface is provided with a groove structure, and forms a grating; the back metal electrode layer covers the second surface of the semiconductor layer; the metal or metalloid layer covers the first surface of the semiconductor layer, and forms a phototube for generating a photocurrent signal having a wide wavelength range and high linearity. An optical sensing structure of narrowband light absorption and a photoelectric conversion structure having a wide wavelength range are directly integrated, and the portable high-precision optical sensing ability is implemented by means of an output mode of a photocurrent.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 14, 2022
    Assignee: JINAN UNIVERSITY
    Inventors: Long Wen, Qin Chen, Baojun Li
  • Patent number: 11362212
    Abstract: A structure includes a transistor including a first source/drain region, a source/drain contact plug over and electrically coupling to the first source/drain region, and a via over and contacting the source/drain contact plug. The via has a bottom portion having a first length, and an upper portion having a second length. The first length is greater than the second length. Both of the first length and the second length are measured in a same direction parallel to a top surface of the source/drain contact plug.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: June 14, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal A Khaderbad, Keng-Chu Lin, Sung-Li Wang
  • Patent number: 11362292
    Abstract: A flexible display device of which esthetic appearance is improved by reducing a bezel is disclosed. The flexible display device comprises a substrate including a display area and a non-display area including a bending area; a link line in the non-display area on the substrate; and a bending connection line in the bending area pf the substrate and connected with the link line, and the bending connection line located between a first buffer layer and a second buffer layer of the flexible display device.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: June 14, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Saemleenuri Lee, SeYeoul Kwon, Dojin Kim
  • Patent number: 11355671
    Abstract: A ring-shaped LED lamp, including at least three LED chips and at least three pins partially located within a package body. The LED chips are connected in series and have two terminal ends connected to form a closed loop, and the pins are led out from connections between the LED chips. A lamp string includes at least one group of lamps and electrically conductive wires connected to multiple lamps, and each group of lamps includes a plurality of the above-described ring-shaped lamps. Also provided is a control circuit applicable for the lamp string. The control circuit includes an input device, a microprocessor, an output circuit, and a lamp string interface connected to the output circuit. The microprocessor receives a signal from the input device, and sends an I/O signal or PWM signal to the output circuit to trigger a voltage level change of the lamp string interface.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 7, 2022
    Inventor: Tit Tsang Chong
  • Patent number: 11355632
    Abstract: A semiconductor structure includes a substrate having a top surface, pillar structures formed on top of the substrate, a gate conductor, a drain/source region and a source/drain region. Each pillar structure of the pillar structures includes a first end and a second end, and the first end is closer to the substrate than the second end. The gate conductor surrounds each of the pillar structures disposed between the first end and the second end. The drain/source region is at the top surface of the substrate and in contact with the first end of a first pillar structure of the pillar structures, and the source/drain region is at the top surface of the substrate and in contact with the first end of a second pillar structure of the pillar structures.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 7, 2022
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventor: Qing Liu
  • Patent number: 11348993
    Abstract: An electronic device includes a flexible substrate and a conductive wire. The flexible substrate includes a first bending region and a side region connected to the first bending region. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. A ratio of a total width of the metal portion disposed in the first bending region to a total width of the metal portion disposed in the side region is in a range from 0.8 to 1.2, and a length of one of the openings in the first bending region is less than or equal to a length of one of the openings in the side region.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: May 31, 2022
    Assignee: InnoLux Corporation
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
  • Patent number: 11349043
    Abstract: The disclosure is related to the technical field of semiconductors, and provides a method for manufacturing a tilted mesa and a method for manufacturing a detector. The method for manufacturing a tilted mesa comprises: coating a photoresist layer on a mesa region of a chip; heating the chip on which the photoresist layer is coated from a first preset temperature to a second preset temperature; performing etching processing on the heated chip, so as to manufacture a mesa having a preset tilting angle; and removing the photoresist layer on the mesa region of the chip after the mesa is manufactured.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: May 31, 2022
    Assignee: The 13th Research Institute of China Electronics Technology Group Corporation
    Inventors: Xingye Zhou, Zhihong Feng, Yuanjie Lv, Xin Tan, Xubo Song, Jia Li, Yulong Fang, Yuangang Wang
  • Patent number: 11335744
    Abstract: An array substrate, a display panel, and a display apparatus. The array substrate includes a base substrate; a first electrode layer formed on the base substrate; a light emitting layer formed on the first electrode layer and including a non-transparent first light emitting region, a second light emitting region, and a transparent third light emitting region; and a second electrode layer formed on the light emitting layer. The first light emitting region includes first light emitting structures. The second light emitting region includes second light emitting structures. The third light emitting region includes third light emitting structures. The second light emitting region is located between the first light emitting region and the third light emitting region. A distribution density of first light emitting structures, a distribution density of second light emitting structures, and a distribution density of third light emitting structures are gradually changed in sequence.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 17, 2022
    Assignee: Yungu (Gu'an) Technology Co., Ltd.
    Inventors: Rusheng Liu, Junhui Lou, Lu Zhang, Jie Sun, Meng Zhang
  • Patent number: 11309245
    Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate having a plurality of contacts, a plurality of plugs positioned above the plurality of contacts, a plurality of metal spacers positioned above the plurality of plugs; and a plurality of air gaps respectively positioned between the plurality of metal spacers.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: April 19, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Kuo-Hui Su
  • Patent number: 11304291
    Abstract: A circuit board according to the present disclosure includes a substrate, a conductor layer arranged on the substrate, a reflective layer arranged on the conductor layer, and a silicone-resin layer arranged on the substrate. The silicone-resin layer is in contact with the conductor layer and the reflective layer. The silicone-resin layer contains equal to or more than 45% by mass of a plurality of fillers. A first filler whose aspect ratio is larger than 5 occupies equal to or more than 5% of 100% of a total number of the fillers.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 12, 2022
    Assignee: KYOCERA CORPORATION
    Inventor: Yuichi Abe
  • Patent number: 11302682
    Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 12, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tsung-Yueh Tsai, Meng-Jen Wang, Yu-Fang Tsai, Meng-Jung Chuang
  • Patent number: 11302849
    Abstract: Phosphor-converted LED side reflectors disclosed herein comprise pigments that are photochemically stable under illumination by light from the pcLED. The pigments absorb light in at least a portion of the spectrum of light emitted by the first phosphor converted LED. The side reflector may also comprise light scattering particles and/or air voids. The pigments, light scattering particles and/or air voids may be homogeneously distributed in the reflector. Alternatively the side reflector may be layered, with the pigments, light scattering particles and/or air voids inhomogeneously distributed in the reflector. The side reflector may comprise phosphor particles.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: April 12, 2022
    Assignee: Lumileds LLC
    Inventors: Grigoriy Basin, Kentaro Shimizu, Brendan Moran, Emma Dohner, Noad Shapiro, Marcel Bohmer
  • Patent number: 11296025
    Abstract: A sensor package includes a carrier, a sensor, an interconnection structure, a conductor and a housing. The sensor is disposed on the carrier. The interconnection structure is disposed on the carrier and surrounds the sensor. The interconnection structure has a first surface facing away from the carrier. The conductor is disposed on the first carrier. The conductor having a first portion covered by the interconnection structure and a second portion exposed from the first surface of the interconnection structure. The housing is disposed on the carrier and surrounds the interconnection structure.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Hsun-Wei Chan, Shih-Chieh Tang
  • Patent number: 11289525
    Abstract: This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: March 29, 2022
    Assignee: Sony Corporation
    Inventors: Hajime Yamagishi, Kiyotaka Tabuchi, Masaki Okamoto, Takashi Oinoue, Minoru Ishida, Shota Hida, Kazutaka Yamane
  • Patent number: 11289490
    Abstract: A programmable array including a plurality cells aligned in a row on a substrate, wherein each of the plurality of cells includes a programmable element and a transistor, wherein the transistor includes a body including a first diffusion region and a second diffusion region on the first diffusion region and separated by a channel and the programmable element is disposed on the second diffusion region. A method of forming an integrated circuit including forming transistor bodies in a plurality rows on a substrate; forming a masking material as a plurality of rows across the bodies; etching the bodies through the masking material to define a width dimension of the transistor bodies; after etching the bodies, patterning each of the plurality of rows of the masking material into a plurality of individual masking units; and replacing each of the plurality of individual masking units with a programmable element.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Van H. Le, Gilbert Dewey, Abhishek A. Sharma
  • Patent number: 11282861
    Abstract: A dynamic logic circuit including a first transistor within a first device stratum of a substrate; and a second transistor within a second device stratum of the substrate that is different from the first device stratum, wherein the first transistor and the second transistor share a common gate electrode. A method including disposing a second semiconductor body of a second transistor on a first semiconductor body of a first transistor in a first device stratum on a substrate, the second semiconductor body defining a second device stratum; and forming a common gate electrode on each of the semiconductor body and the second semiconductor body.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Donald W. Nelson, Rishabh Mehandru
  • Patent number: 11276791
    Abstract: In an edge incident type semiconductor light receiving device that reflects light incident parallel to the main surface of the semiconductor substrate opaque to the incident light to the light receiving section on the main surface side, a light guide section is formed to expose the light receiving section along the light incident direction from the light incident side end of the semiconductor substrate, and in order to guide the light incident on the light guide section to the light receiving section, a light reflection section having a given crossing angle with the main surface is provided at the end of the light guide section in the light incident direction.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: March 15, 2022
    Assignee: KYOTO SEMICONDUCTOR CO., LTD.
    Inventors: Takatomo Isomura, Etsuji Omura
  • Patent number: 11271111
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain feature in the substrate, protruding from the substrate, and on a sidewall surface of the gate structure. The semiconductor device structure also includes an insulating barrier structure in the substrate and partially covering the bottom and sidewalls of the source/drain feature.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Chun Kuan, I-Chih Chen, Chih-Mu Huang, Fu-Tsun Tsai, Sheng-Lin Hsieh, Kuan-Jung Chen
  • Patent number: 11271052
    Abstract: The present disclosure provides a display substrate including a display area and a fingerprint recognition area. The display area includes a low-temperature polycrystalline oxide structure, an organic light-emitting layer, a cathode layer, and an anode layer that are sequentially stacked. The fingerprint recognition area includes an under-screen fingerprint recognition structure. The low-temperature polycrystalline oxide structure and the under-screen fingerprint recognition structure are disposed on a same layer. The under-screen fingerprint recognition structure includes the cathode layer and the organic light-emitting layer.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: March 8, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Hong Gao, Mugyeom Kim