Patents Examined by Suberr L Chi
  • Patent number: 12161037
    Abstract: A display panel disposes a first display area and a second display area. The display panel includes a plurality of OLED pixel units disposed in the first display area, and a plurality of Micro LED pixel units disposed in the second display area. By replacing the OLED pixel units corresponding to the under-screen camera or used to display a fixed picture with the Micro LED pixel units, the image quality of an under-screen camera can be improved, and the burning screen problem caused by displaying the same picture for a long time can be solved.
    Type: Grant
    Filed: November 11, 2019
    Date of Patent: December 3, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Fancheng Liu, Guowei Zha
  • Patent number: 12148841
    Abstract: Embodiments of the present disclosure relate to a thin film transistor array substrate and display device in which a semiconductor layer has a heterogeneous conductorization structure including heterogeneous conductorization portions having different electrical conductivity, and the gate insulator layer is not etched enough to expose the semiconductor layer between the source electrode part and the gate electrode part and between the drain electrode part and the gate electrode part, so that the possibility of damage to the semiconductor layer can be eliminated or reduced.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: November 19, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: Chanyong Jeong, Juheyuck Baeck, Dohyung Lee, Younghyun Ko
  • Patent number: 12148868
    Abstract: Light emitting diode (LED) constructions comprise an LED having a pair of electrical contacts along a bottom surface. A lens is disposed over the LED and covers a portion of the LED bottom surface. A pair of electrical terminals is connected with respective LED contacts, are sized larger than the contacts, and connect with the lens material along the LED bottom surface. A wavelength converting material may be interposed between the LED and the lens. LED constructions may comprise a number of LEDs, where the light emitted by each LED differs from one another by about 2.5 nm or less. LED constructions are made by attaching 2 or more LEDs to a common wafer by adhesive layer, forming a lens on a wafer level over each LED to provide a rigid structure, removing the common wafer, forming the electrical contacts on a wafer level, and then separating the LEDs.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: November 19, 2024
    Assignee: Bridgelux, Inc.
    Inventors: Vladimir A. Odnoblyudov, R. Scott West
  • Patent number: 12148711
    Abstract: Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: November 19, 2024
    Inventors: Owen R. Fay, Dong Soon Lim, Randon K. Richards, Aparna U. Limaye
  • Patent number: 12142705
    Abstract: The disclosure relates to a method for regulating photocurrent of IGZO based on a two-dimensional black phosphorus material, and belongs to the field of semiconductor devices. The disclosure provides a method for preparing an IGZO-black phosphorus heterostructure by dry transfer technology, and by changing the contact mode between IGZO and black phosphorus, photocurrent response of the IGZO to different laser light wavelengths can be regulated. In the method, both a channel and electrodes of the IGZO are magnetron sputtered by means of masks, and the method has good repeatability and can realize preparation of large-area multi-devices. A black phosphorus sample is prepared by a mechanical exfoliation method, and has controllable thickness and size. A heterojunction is prepared by dry transfer technology, and the technology is easy to operate and highly controllable. The disclosure is beneficial to promote development of IGZO thin films in the micro-nano field and the semiconductor industry.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: November 12, 2024
    Assignee: Jiangnan University
    Inventors: Haiyan Nan, Daqing Li, Feng Shao, Shaoqing Xiao, Xiaofeng Gu
  • Patent number: 12142635
    Abstract: A semiconductor device includes first channel layers disposed over a substrate, a first source/drain region disposed over the substrate, a gate dielectric layer disposed on and wrapping each of the first channel layers, a gate electrode layer disposed on the gate dielectric layer and wrapping each of the first channel layers, and a liner semiconductor layer disposed between the first channel layers and the first source/drain region.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: November 12, 2024
    Assignee: Parabellum Strategic Opportunities Fund LLC
    Inventors: Ka-Hing Fung, Kuo-Cheng Ching, Ying-Keung Leung
  • Patent number: 12137594
    Abstract: A display panel and driving method thereof and a display apparatus. The display panel has a first display area and a second display area, a transmittance of the first display area is greater than a transmittance of the second display area, the display panel includes an array substrate, and a light-emitting layer arranged on the array substrate and includes a first sub-pixel density distribution area arranged corresponding to the first display area, a second sub-pixel density distribution area arranged corresponding to the second display area and a third sub-pixel density distribution area on at least one of the first display area and the second display area and arranged adjacent to a boundary between the first display area and the second display area, in which a third sub-pixel distribution density is between a first sub-pixel distribution density and a second sub-pixel distribution density.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: November 5, 2024
    Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd.
    Inventors: Junhui Lou, Fengzhang Hu
  • Patent number: 12136678
    Abstract: A photodetector includes a photodiode that has a germanium junction formed between an n-doped region and a p-doped region. The germanium junction is formed to have an input interface at a light input end of the germanium junction. The input interface has a substantially flat shape or a convex-faceted shape. The photodetector also includes an input waveguide connected to the input interface of the germanium junction. The input waveguide has a substantially linear shape along a lengthwise centerline of the input waveguide. The input waveguide is oriented so that the lengthwise centerline of the input waveguide is positioned at a non-zero angle relative to input interface of the germanium junction.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: November 5, 2024
    Assignee: Ayar Labs, Inc.
    Inventors: Dries Vercruysse, John M. Fini
  • Patent number: 12125933
    Abstract: A device for detecting UV radiation, comprising: a SiC substrate having an N doping; a SiC drift layer having an N doping, which extends over the substrate; a cathode terminal; and an anode terminal. The anode terminal comprises: a doped anode region having a P doping, which extends in the drift layer; and an ohmic-contact region including one or more carbon-rich layers, in particular graphene and/or graphite layers, which extends in the doped anode region. The ohmic-contact region is transparent to the UV radiation to be detected.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: October 22, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Simone Rascuná, Gabriele Bellocchi, Paolo Badalá, Isodiana Crupi
  • Patent number: 12127432
    Abstract: The present application discloses a display panel and a display apparatus, where the display panel has a first display area and a second display area, and a boundary is provided between the first display area and the second display area, and the display panel comprises: a pixel unit layer comprising a first pixel group positioned in a first display area, a second pixel group positioned in a second display area and a third pixel group positioned in at least one of the first display area and the second display area and adjacent to a boundary, wherein the first pixel group comprises a plurality of first pixel units, and the first pixel unit comprises a first sub-pixel and a first virtual sub-pixel; the third pixel group comprises two third pixel units which correspond to one first pixel unit.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: October 22, 2024
    Assignee: KunShan Go-Visionox Opto-Electronics Co., Ltd
    Inventors: Lu Zhang, Junhui Lou, Feng Chen, Yong Zhu
  • Patent number: 12119421
    Abstract: A photodetector including: an amplification region that includes a PN junction provided in a depth direction in a semiconductor layer and that is to be electrically coupled to a cathode; a separation region that defines a pixel region including the amplification region; a hole accumulation region that is provided along a side surface of the separation region and that is to be electrically coupled to an anode; and a gate electrode provided in a region between the amplification region and the hole accumulation region and stacked over the semiconductor layer with a gate insulating film interposed therebetween.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: October 15, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Katsuhisa Tanaka, Yusuke Otake
  • Patent number: 12120912
    Abstract: The present disclosure relates a display panel. The display device includes a plurality of first pixels disposed in a first area, a plurality of second pixels disposed in a second area surrounded by the first area, and a plurality of third pixels disposed in a third area between the first area and the second area.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: October 15, 2024
    Assignee: LG Display Co., Ltd.
    Inventors: SungJin Park, SangBin Lee
  • Patent number: 12114530
    Abstract: According to one embodiment, a display device comprises a pixel circuit, an insulating layer that covers the pixel circuit and includes a first trench, a first electrode disposed on the insulating layer, an organic layer disposed on the first electrode, a second electrode disposed on the organic layer, and a first filling layer that fills at least a part of the first trench. An end portion of the first electrode is located inside the first trench and is covered with the first filling layer.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: October 8, 2024
    Assignee: Japan Display Inc.
    Inventor: Hiroumi Kinjo
  • Patent number: 12100658
    Abstract: A method of making a 3D multilayer semiconductor device, the method comprising: providing a first substrate comprising a first level, said first level comprising a first single crystal silicon layer; providing a second substrate comprising a second level, said second level comprising a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of said second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer; forming a plurality of second transistors each comprising a single crystal channel; forming a plurality of metal layers interconnecting said plurality of second transistors; and then performing a bonding of said second level onto said first level, wherein performing said bonding comprises making oxide-to-oxide bond zones, and performing removal of a majority of said second single crystal silicon layer.
    Type: Grant
    Filed: March 31, 2024
    Date of Patent: September 24, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Patent number: 12100725
    Abstract: Light detecting structures comprising a Si base having a pyramidal shape with a wide incoming light-facing pyramid bottom and a narrower pyramid top and a Ge photodiode formed on the Si pyramid top, wherein the Ge photodiode is operable to detect light in the short wavelength infrared range, and methods for forming such structures. A light detecting structure as above may be repeated spatially and fabricated in the form of a focal plane array of Ge photodetectors on silicon.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: September 24, 2024
    Assignee: TriEye Ltd.
    Inventors: Avraham Bakal, Uriel Levy, Omer Kapach
  • Patent number: 12100620
    Abstract: In a processing method for a wafer with a mark formed in an outer peripheral portion thereof, a frame unit having the wafer, a tape, and a ring frame is provided, a set of processing conditions for processing the wafer is selected, and a representative image associated with the set of processing conditions is displayed on a display unit. The ring frame includes a notch formed in an outer periphery thereof. In the frame unit, the mark and the notch are in a positional relationship set in accordance with the set of processing conditions. The positional relationship is presented in the representative image.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: September 24, 2024
    Assignee: DISCO CORPORATION
    Inventor: Yoshinobu Saito
  • Patent number: 12087873
    Abstract: A photodiode is formed in a semiconductor substrate of a first conductivity type. The photodiode includes a first region having a substantially hemispherical shape and a substantially hemispherical core of a second conductivity type, different from the first conductivity type, within the first region. An epitaxial layer covers the semiconductor substrate and buries the first region and core.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: September 10, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Antonin Zimmer, Dominique Golanski, Raul Andres Bianchi
  • Patent number: 12080821
    Abstract: The present invention discloses a novel silicon carbide-based lateral PN junction extreme ultraviolet detector with enhanced detection performance based on selective-area ion implantation, including an N-type ohmic contact lower electrode, an N-type substrate and a lightly-doped epitaxial layer which are connected sequentially from bottom to top, where the lightly-doped epitaxial layer is an N-type lightly-doped epitaxial layer or a P-type lightly-doped epitaxial layer; in a case that the lightly-doped epitaxial layer is an N-type or P-type lightly-doped epitaxial layer, a P-type or N-type well region is formed on the surface of the N-type or P-type lightly-doped epitaxial layer through the selective-area ion implantation, a P-type or N-type ohmic contact upper electrode is arranged on the P-type or N-type well region, and the P-type or N-type ohmic contact upper electrode is provided with a metal conductive electrode along its periphery.
    Type: Grant
    Filed: February 27, 2024
    Date of Patent: September 3, 2024
    Assignee: NANJING UNIVERSITY
    Inventors: Hai Lu, Dong Zhou, Weizong Xu
  • Patent number: 12068276
    Abstract: Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: August 20, 2024
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giovanni Graziosi, Michele Derai
  • Patent number: 12068421
    Abstract: A light shielding structure of an optical circuit of the present invention uses a part of the structure of the light reception element itself to suppress stray light. A stepped electrode that covers an upper surface and side surface of a first semiconductor layer constituting a light absorption portion of the light reception element is formed at a height substantially equal to that of an optical waveguide in the optical circuit, and the light absorption portion of the light reception element is shielded from stray light by a wall-shaped or column-shaped wiring electrode extending substantially perpendicularly to a surface layer of the optical circuit. The light shielding structure of the present invention uses a part of the configuration of the light reception element, is formed integrally with the light reception element, and also has an aspect of the invention of the light reception element.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: August 20, 2024
    Assignees: NTT ELECTRONICS CORPORATION, NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Keiichi Morita, Atsushi Murasawa, Hiroki Kawashiri, Yusuke Nasu