Patents Examined by Sue A. Purvis
  • Patent number: 11127859
    Abstract: A semiconductor device includes a channel structure, a dielectric structure, a gate structure, a first conductive structure, and a second conductive structure. The channel structure has a top surface, a bottom surface, and a sidewall extending from the top surface to the bottom surface. The first conductive structure is disposed on the bottom surface of the channel structure and includes a body portion and at least one convex portion, and a top surface of the convex portion is higher than a top surface of the body portion. The second conductive structure is disposed on the top surface of the channel structure and includes a body portion and at least one convex portion, and a bottom surface of the body portion is higher than a bottom surface of the convex portion.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: September 21, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Jhen-Yu Tsai
  • Patent number: 11114431
    Abstract: Electrostatic discharge (ESD) protection device is provided. An ESD device includes a substrate having an input region; a plurality of fins on the substrate in the input region; a well region, doped with first-type ions, in the plurality of fins and in the substrate; an epitaxial layer on each fin in the input region; a drain region, doped with second-type ions, in a top portion of each fin and in the epitaxial layer; an extended drain region, doped with the second-type ions, in a bottom portion of each fin to connect to the drain region and in a portion of the substrate, in the input region; and a counter-doped region, doped with the first-type ions, in a portion of the substrate between two adjacent fins to insulate adjacent extended drain regions.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: September 7, 2021
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Yong Li
  • Patent number: 11114594
    Abstract: A radiation emitting device comprising light scattering particles of different sizes that at least partially surround an emitter, improving the spatial color mixing and color uniformity of the device. Multiple sizes of light scattering particles are dispersed in a medium to at least partially surround a single- or multiple-chip polychromatic emitter package. The different sizes of light scattering particles interact with corresponding wavelength ranges of emitted radiation. Thus, radiation emitted over multiple wavelength ranges or sub-ranges can be efficiently scattered to eliminate (or intentionally create) spatially non-uniform color patterns in the output beam.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: September 7, 2021
    Assignee: CreeLED, Inc.
    Inventor: Arpan Chakraborty
  • Patent number: 11114596
    Abstract: A light-emitting device includes: a light-emitting element; a coating member that covers the light-emitting element; and two external connection electrodes exposed form a first surface of the coating member. Each of the external connection electrodes includes an electrode buried in the coating member; and a metal layer formed on the electrode. A surface of each of the metal layers is exposed from the first surface of the coating member. The first surface of the coating member includes a plurality of grooves between the external connection electrodes.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: September 7, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Yoshikazu Matsuda, Ryo Suzuki
  • Patent number: 11107813
    Abstract: A semiconductor device includes first and second Fin FETs and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending in a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending in the second direction. When viewed from above, an end shape the separation plug has a concave curved shape, while an end of the first gate electrode abutting the separation plug has a convex curved shape.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chih-Han Lin
  • Patent number: 11101211
    Abstract: An approach to creating a semiconductor chip including a semiconductor substrate with one or more topside metal layers and one or more backside metal layers. The approach creates the semiconductor chip with one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate and one or more inductors in the one or more backside metal layer. Furthermore, the approach creates the semiconductor chip with one or more through silicon vias extending through the semiconductor substrate connecting the one or more inductors in the one or more backside metal layers and the one or more semiconductor devices with wiring interconnects in the one or more topside metal layers on the semiconductor substrate.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 24, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hassan Naser, Calist Friedman, Matthew A. Cooke, Daniel L. Stasiak
  • Patent number: 11087987
    Abstract: In an embodiment, a method includes: forming a first fin extending from a substrate, the substrate including silicon, the first fin including silicon germanium; forming an isolation region around the first fin, an oxide layer being formed on the first fin during formation of the isolation region; removing the oxide layer from the first fin with a hydrogen-based etching process, silicon at a surface of the first fin being terminated with hydrogen after the hydrogen-based etching process; desorbing the hydrogen from the silicon at the surface of the first fin to depassivate the silicon; and exchanging the depassivated silicon at the surface of the first fin with germanium at a subsurface of the first fin.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun Ma, Yi-Cheng Li, Pin-Ju Liang, Cheng-Po Chau, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen, Cheng-Hsiung Yen
  • Patent number: 11075248
    Abstract: An organic light emitting display apparatus includes a first electrode on a substrate and a plurality of organic layers on the first electrode and including a first region and a second region. The organic light emitting display apparatus further includes a second electrode on the plurality of organic layers. A thickness of the plurality of organic layers in the first region can be different from a thickness of the plurality of organic layers in the second region.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 27, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: MiKyung Park, YongCheol Kim
  • Patent number: 11075173
    Abstract: A semiconductor package includes a first die having a first substrate, an interconnect structure overlying the first substrate and having multiple metal layers with vias connecting the multiple metal layers, a seal ring structure overlying the first substrate and along a periphery of the first substrate, the seal ring structure having multiple metal layers with vias connecting the multiple metal layers, the seal ring structure having a topmost metal layer, the topmost metal layer being the metal layer of the seal ring structure that is furthest from the first substrate, the topmost metal layer of the seal ring structure having an inner metal structure and an outer metal structure, and a polymer layer over the seal ring structure, the polymer layer having an outermost edge that is over and aligned with a top surface of the outer metal structure of the seal ring structure.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsiang Tseng, Yu-Feng Chen, Cheng Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Kuo-Ching Hsu, Hong-Seng Shue, Ming-Hong Cha, Chao-Yi Wang, Mirng-Ji Lii
  • Patent number: 11069818
    Abstract: A semiconductor device is provided. The semiconductor device includes: a first wire pattern disposed on a substrate and extending in a first direction; a first gate electrode surrounding the first wire pattern and extending in a second direction, the first direction intersecting the second direction perpendicularly; a first transistor including the first wire pattern and the first gate electrode; a second wire pattern disposed on the substrate and extending in the first direction; a second gate electrode surrounding the second wire pattern and extending in the second direction; and a second transistor including the second wire pattern and the second gate electrode, wherein a width of the first wire pattern in the second direction is different from a width of the second wire pattern in the second direction.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: July 20, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myung Gil Kang, Dong Won Kim, Geum Jong Bae, Kwan Young Chun
  • Patent number: 11061794
    Abstract: Methods, systems, and computer readable mediums for optimizing data processing are disclosed. According to one exemplary embodiment, a method for optimizing data processing includes receiving data usage information associated with at least one user-defined key performance indicator (KPI), determining, using the data usage information, optimization information for optimizing data processing, and providing the optimization information to at least one resource.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: July 13, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventor: Ying Victor Zhang
  • Patent number: 11056513
    Abstract: The present disclosure discloses a thin film transistor array substrate, a display panel and a display device. The array substrate includes a substrate and an electrostatic discharge circuit layer, and the electrostatic discharge circuit layer is disposed in the non-display area at a side of the substrate and includes a conductive circuit disposed around the display area and electrostatic discharge devices electrically connected with the conductive circuit. The electrostatic discharge device includes a plurality of electrostatic discharge units disposed at intervals, one end of each of the electrostatic discharge units is connected with an edge of the substrate and the other end thereof is connected with the conductive circuit.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: July 6, 2021
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventors: Xiaohui Nie, Jiawei Zhang
  • Patent number: 11056431
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and first fuse branches and second fuse branches are formed in the substrate, in which the first fuse branches and the second fuse branches are separated by a shallow trench isolation (STI) and the second fuse branches include different sizes. Next, fuse elements are formed to connect the first fuse branches and the second fuse branches.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: July 6, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventor: Yukihiro Nagai
  • Patent number: 11043602
    Abstract: Provided is a Schottky barrier diode which is configured from a Ga2O3-based semiconductor, and has a lower rising voltage than a conventional one. In one embodiment, the Schottky barrier diode 1 is provided which has: a semiconductor layer 10 configured from a Ga2O3-based single crystal; an anode electrode 11 which forms a Schottky junction with the semiconductor layer 10, and has a portion which contacts the semiconductor layer 10 and is composed of Fe or Cu; and a cathode electrode 12.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: June 22, 2021
    Assignees: Tamura Corporation, Novel Crystal Technology, Inc.
    Inventors: Kohei Sasaki, Daiki Wakimoto, Yuki Koishikawa, Quang Tu Thieu
  • Patent number: 11038033
    Abstract: The present subject matter relates to an integrated circuit. The integrated circuit includes a first metal layer and a second metal layer capacitively coupled to the first metal layer through a dielectric layer. Further, the second metal layer includes an electron leakage path to provide for leakage of charge from the second metal layer in a predetermined leak time period.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: June 15, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Reynaldo V Villavelez, Ning Ge, Mun Hooi Yaow, Erik D Ness, David B Novak
  • Patent number: 11038084
    Abstract: A light-emitting device includes a first light-emitting element, a second light-emitting element having a peak emission wavelength different from that of the first light-emitting element, a light-guide member covering a light extracting surface and lateral surfaces of the first light-emitting element and a light extracting surface and lateral surfaces of the second light-emitting element, and a wavelength conversion layer continuously covering the light extracting surface of each of the first and second light-emitting elements and disposed apart from each of the first and second light-emitting elements, and a first reflective member covering outer lateral surfaces of the light-guide member. An angle defined by an active layer of the first light-emitting element and an active layer of the second light-emitting element is less than 180° at a wavelength conversion layer side.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 15, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Toru Hashimoto, Takuya Nakabayashi
  • Patent number: 11024732
    Abstract: A lateral trench MOSFET comprises an insulating layer buried in a substrate, a body region in the substrate, an isolation region in the substrate, a first drain/source region over the body region, a second drain/source region in the substrate, wherein the first drain/source region and the second drain/source region are on opposing sides of the isolation region, a drift region comprising a first drift region of a first doping density formed between the second drain/source region and the insulating layer, wherein the first drift region comprises an upper portion surrounded by isolation regions and a lower portion and a second drift region of a second doping density formed between the isolation region and the insulating layer, wherein a height of the second drift region is equal to a height of the lower portion of the first drift region.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Po-Yu Chen
  • Patent number: 11018182
    Abstract: A pixel structure includes a light emitting diode chip and a light blocking structure. The light emitting diode chip includes a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first electrode, and K second electrodes. The active layer is located on the P-type semiconductor layer. The N-type semiconductor layer is located on the active layer. The N-type semiconductor layer has a first top surface that is distant from the active layer. The first electrode is electrically connected to the P-type semiconductor layer. The light blocking structure is located in the light emitting diode chip and defines K sub-pixel regions. The active layer and the N-type semiconductor layer are divided into K sub-portions respectively corresponding to the K sub-pixel regions by the light blocking structure. The K sub-pixel regions share the P-type semiconductor layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 25, 2021
    Assignee: Lextar Electronics Corporation
    Inventors: Yi-Jyun Chen, Li-Cheng Yang, Yu-Chun Lee, Shiou-Yi Kuo, Chih-Hao Lin
  • Patent number: 11011653
    Abstract: Provided is a Schottky barrier diode which is configured from a Ga2O3-based semiconductor, and has a lower rising voltage than a conventional one. In one embodiment, the Schottky barrier diode 1 is provided which has: a semiconductor layer 10 configured from a Ga2O3-based single crystal; an anode electrode 11 which forms a Schottky junction with the semiconductor layer 10, and has a portion which contacts the semiconductor layer 10 and is composed of Fe or Cu; and a cathode electrode 12.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: May 18, 2021
    Assignees: Tamura Corporation, Novel Crystal Technology, Inc.
    Inventors: Kohei Sasaki, Daiki Wakimoto, Yuki Koishikawa, Quang Tu Thieu
  • Patent number: 11011514
    Abstract: Certain embodiments include a cubic boron nitride (c-BN) device. The c-BN device includes a n/n+ Schottky diode and a n/p/n+ bipolar structure. The n/n+ Schottky diode and the /p/n+ bipolar structure are on a single-crystal diamond platform.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: May 18, 2021
    Assignee: North Carolina State University
    Inventor: Jagdish Narayan