Abstract: A power MOSFET IC device including a source-down enhancement mode transistor formed in a semiconductor substrate and a depletion mode transistor formed in a doped region of the semiconductor substrate. A gate terminal of the depletion mode transistor is formed over at least a portion of the doped region as a field plate that is switchably connectable to a source terminal of the source-down enhancement mode transistor. A control circuit may be provided to facilitate a connection between the gate terminal of the depletion mode transistor and the source terminal of the source-down enhancement mode transistor when the power MOSFET integrated circuit is in an OFF state. The control circuit may also be configured to facilitate connection of the gate terminal of the depletion mode transistor to a gate terminal of the source-down enhancement mode FET device or to an external driver that provides a reference voltage, when the power MOSFET is in an ON state.

Abstract: A MEMS element within a semiconductor device is enclosed within a cavity bounded at least in part by hydrogen-permeable material. A hydrogen barrier is formed within the semiconductor device to block propagation of hydrogen into the cavity via the hydrogen-permeable material.

Abstract: An array substrate, display panel and display device. The array substrate includes: a source-drain metal layer, a pixel electrode layer, an insulation layer located between the source-drain metal layer and the pixel electrode layer, and a plurality of sub-pixels distributed in an array. Each sub-pixel corresponds to a drain electrode contained in source-drain metal layer, a pixel electrode contained in pixel electrode layer, and a drain through-hole defined in insulation layer. The pixel electrode is connected to the drain electrode via the drain through-hole. For any one row of the array, in a column direction, each drain electrode through hole is located at the same side of the sub-pixel 10 corresponding to the drain electrode through hole. The sub-pixels includes two adjacent support sub-pixels in a row direction, and the two drain through-holes respectively corresponding to the two adjacent support sub-pixels are unaligned in the column direction.

Abstract: A transistor includes a gate structure over a substrate, wherein the substrate includes a channel region under the gate structure. The transistor further includes a source in the substrate adjacent a first side of the gate structure. The transistor further includes a drain in the substrate adjacent a second side of the gate structure, wherein the second side of the gate structure is opposite the first side of the gate structure. The transistor further includes a first lightly doped drain (LDD) region adjacent the source. The transistor further includes a second LDD region adjacent the drain. The transistor further includes a doping extension region adjacent the first LDD region.

Abstract: A group-Ill nitride stacked body includes a substrate, an n-type first AlGaN layer expressed by the composition formula AlXGa1-XN (0<X?1), and a second AlGaN layer which is disposed between the substrate and the n-type first AlGaN layer and which is expressed by the composition formula AlYGa1-YN (0.5<Y?1, where Y<X). A group-III nitride light-emitting element comprises an active layer which is disposed on the n-type first AlGaN layer of the group-Ill nitride stacked body and which includes at least one well layer. The well layer of the active layer is an AlGaN layer expressed by the composition formula AlWGa1-WN (0<W<1), where the Al composition W is such that W?Y.

Abstract: The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

Abstract: A current sensor integrated circuit includes a lead frame having a primary conductor and at least one secondary lead, a semiconductor die disposed adjacent to the primary conductor, an insulation structure disposed between the primary conductor and the semiconductor die, and a non-conductive insulative material enclosing the semiconductor die, the insulation structure, a first portion of the primary conductor, and a first portion of the at least one secondary lead to form a package. The first portion of the at least one secondary lead (between a first end proximal to the primary conductor and a second end proximal to the second, exposed portion of the at least one secondary lead) has a thickness that is less than a thickness of the second, exposed portion of the least one secondary lead. A distance between the second, exposed portion of the primary conductor and the second, exposed portion of the at least one secondary lead is at least 7.2 mm.

Abstract: A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.

Abstract: A nonvolatile memory device includes an active region extending in a first direction and including a source region and a drain region that are respectively disposed at both ends of the active region, a gate electrode pattern extending in a second direction and disposed between the source region and the drain region, wherein the second direction extends across the first direction, a gate insulation pattern disposed between the gate electrode pattern and the active region, a source contact plug and a drain contact plug respectively coupled to the source region and the drain region, and a coupling contact plug disposed over the gate electrode pattern and insulated from the gate electrode pattern.

Abstract: A light emitting apparatus includes an electrically insulating base member; a first electrically conductive pattern portion and a second electrically conductive pattern portion formed on an upper surface of the base member; a plurality of intermediate electrically conductive pattern portions arranged between the first and second electrically conductive pattern portions; at least one light emitting device mounted on at least one of the intermediate electrically conductive pattern portions; a protection element mounted on the first and second electrically conductive pattern portions; and a resin portion disposed around the at least one light emitting device such that (i) the first and second electrically conductive pattern portions are partially covered by the resin portion and partially exposed from the resin portion, and (ii) the protection element is covered by the resin portion.

Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer; wherein the plurality of scribe lines protrudes from a third surface of the second wafer, and the third surface is between the first surface and the second surface.

Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

Abstract: A microfluidic chip suitable for detecting a microdroplet includes a first component, a second component, a channel layer, and a semiconductor chip. The first component includes a first substrate, a first electrode layer, and a first dielectric layer, wherein the first electrode layer is located between the first substrate and the first dielectric layer. The second component is disposed opposite to the first component and includes a second substrate, a second electrode layer, and a second dielectric layer. The channel layer is located between the first component and the second component. The semiconductor chip is disposed at one side of the first substrate and is exposed to the channel layer to assist in treating or detecting a sample or microdroplet. The microdroplet in the sample entering the channel layer is reacted with the semiconductor chip, and thus the sample is detected.

Abstract: A manufacturing method of an LED package structure includes the steps as follows: providing an LED package structure assembly, which has a substrate layer, an LED chip set located on the substrate layer, and an encapsulating gel layer covering the LED chip set; taking a first blade to saw the LED package structure assembly from the encapsulating gel layer to the substrate layer until a plurality of sawing grooves are formed on the substrate layer; and taking a second blade to saw the LED package structure assembly along each sawing groove until the second blade passes through the substrate layer, thereby forming a plurality of LED package structures separated from each other. Wherein a hardness of the first blade is greater than that of the second blade, and a thickness of the second blade is less than that of the first blade.

Abstract: A semiconductor substrate having a through-silicon via with an air gap interposed between the through-silicon via and the semiconductor substrate is provided. An opening is formed partially through the semiconductor substrate. The opening is first lined with a first liner and then the opening is filled with a conductive material. A backside of the semiconductor substrate is thinned to expose the first liner, which is subsequently removed and a second liner formed with a low-k or extra low-k dielectric is formed in its place.

Abstract: A method for manufacturing a flash memory device on a substrate may include: preparing the substrate with shallow trench isolation to define active sections; depositing a floating gate oxide layer on the prepared substrate; depositing a floating gate polysilicon layer on the floating gate oxide layer; polishing the floating gate polysilicon layer to isolate a plurality of floating gates above the active sections of the substrate; depositing a silicon nitride layer on top of the plurality of floating gates; patterning and etching the silicon nitride layer to create silicon nitride features; depositing a set of oxide spacers along sides of the silicon nitride features; implanting a source junction into the substrate beneath the individual floating gates; removing the floating gate polysilicon layer except where beneath individual oxide spacers, then removing the set of oxide spacers; depositing an inter-poly layer on top of the remaining floating gates; depositing a second polysilicon layer on top of the inter-

Abstract: A method to make light-emitting diode (LED) units include arranging LEDs in a pattern, forming an optically transparent spacer layer over the LEDs, forming an optically reflective layer over the LEDs, and singulating the LEDs into LED units. The method may further include, after forming the optically transparent spacer layer and before singulating the LEDs, forming a secondary light-emitting layer that conforms to the LEDs, cutting the LEDs to form LED groups having a same arrangement, spacing the LED groups on a support, and forming the optically reflective layer in spaces between the LED groups.